Datasheet

 2013-2015 Microchip Technology Inc. DS40001723D-page 193
PIC12(L)F1571/2
21.4.2 AUTO-BAUD OVERFLOW
During the course of Automatic Baud Detection, the
ABDOVF bit of the BAUDCON register will be set if the
baud rate counter overflows before the fifth rising edge
is detected on the RX pin. The ABDOVF bit indicates
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPBRGH:SPBRGL register
pair. The overflow condition will set the RCIF flag. The
counter continues to count until the fifth rising edge is
detected on the RX pin. The RCIDL bit will remain false
(‘0’) until the fifth rising edge, at which time, the RDICL
bit will set. If the RCREG is read after the overflow
occurs, but before the fifth rising edge, the fifth rising
edge will set the RCIF again.
Terminating the auto-baud process early to clear an
overflow condition will prevent proper detection of the
Sync character fifth rising edge. If any falling edges of
the Sync character have not yet occurred when the
ABDEN bit is cleared, then those will be falsely
detected as Start bits. The following steps are
recommended to clear the overflow condition:
1. Read RCREG to clear RCIF.
2. If RCIDL is zero, then wait for RCIF and repeat
Step 1.
3. Clear the ABDOVF bit.
21.4.3 AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The auto-wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
The auto-wake-up feature is enabled by setting the WUE
bit of the BAUDCON register. Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 21-7), and asynchronously if
the device is in Sleep mode (Figure 21-8). The interrupt
condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
21.4.3.1 Special Considerations
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled, the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all ‘0’s. This must be ten or more bit times; 13-bit
times are recommended for LIN bus or any number of
bit times for standard RS-232 devices.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.