Datasheet

 2013-2015 Microchip Technology Inc. DS40001723D-page 175
PIC12(L)F1571/2
21.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer, inde-
pendent of device program execution. The EUSART,
also known as a Serial Communications Interface
(SCI), can be configured as a full-duplex asynchronous
system or half-duplex synchronous system.
Full-Duplex mode is useful for communications with
peripheral systems, such as CRT terminals and per-
sonal computers. Half-Duplex Synchronous mode is
intended for communications with peripheral devices,
such as A/D or D/A integrated circuits, serial EEPROMs
or other microcontrollers. These devices typically do not
have internal clocks for baud rate generation and require
the external clock signal provided by a master
synchronous device.
The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock polarity in synchronous
modes
• Sleep operation
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 21-1 and Figure 21-2.
FIGURE 21-1: EUSART TRANSMIT BLOCK DIAGRAM
TXREG register
8
Pin Buffer
and Control
TXIF
TRMT
TX9D
Data bus
8
TXIE
Interrupt
TX/CK
TX9
TXEN
Transmit Shift Register (TSR)
(8) 0
MSb LSb
÷ n
Multiplier x4
SYNC
BRGH
BRG16
x16 x64
1
1
1
1
1
x
x
x0
0
0
0
0
0
0
n
+ 1
SPBRGH SPBRGL
Baud Rate Generator
F
OSC
BRG16
Rev. 10-000113B
7/14/2015