Datasheet

 2013-2015 Microchip Technology Inc. DS40001723D-page 173
PIC12(L)F1571/2
20.5 Register Definitions: Timer2 Control
TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
REGISTER 20-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 = 1:1 Postscaler
0001 = 1:2 Postscaler
0010 = 1:3 Postscaler
0011 = 1:4 Postscaler
0100 = 1:5 Postscaler
0101 = 1:6 Postscaler
0110 = 1:7 Postscaler
0111 = 1:8 Postscaler
1000 = 1:9 Postscaler
1001 = 1:10 Postscaler
1010 = 1:11 Postscaler
1011 = 1:12 Postscaler
1100 = 1:13 Postscaler
1101 = 1:14 Postscaler
1110 = 1:15 Postscaler
1111 = 1:16 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
10 = Prescaler is 16
11 = Prescaler is 64
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE1 TMR1GIE ADIE RCIE
(1)
TXIE
(1)
— —TMR2IETMR1IE 75
PIR1
TMR1GIF ADIF RCIF
(1)
TXIF
(1)
— —TMR2IFTMR1IF 78
PR2 Timer2 Module Period Register 171*
T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 173
TMR2 Holding Register for the 8-bit TMR2 Count 171*
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
* Page provides register information.
Note 1: PIC12(L)F1572 only.