PIC12(L)F1571/2 8-Pin MCU with High-Precision 16-Bit PWMs Description: PIC12(L)F1571/2 microcontrollers combine the capabilities of 16-bit PWMs with Analog to suit a variety of applications. These devices deliver three 16-bit PWMs with independent timers for applications where high resolution is needed, such as LED lighting, stepper motors, power supplies and other general purpose applications.
PIC12(L)F1571/2 Analog Peripherals: Clocking Structure: • 10-Bit Analog-to-Digital Converter (ADC): - Up to four external channels - Conversion available during Sleep • Comparator: - Low-Power/High-Speed modes - Fixed Voltage Reference at (non)inverting input(s) - Comparator outputs externally accessible - Synchronization with Timer1 clock source - Software hysteresis enable • 5-Bit Digital-to-Analog Converter (DAC): - 5-bit resolution, rail-to-rail - Positive reference selection - Unbuffered I/O pin outp
PIC12(L)F1571/2 PIN DIAGRAMS 1 RA5 2 RA4 3 RA3/MCLR/VPP 4 PIC12(L)F1572 VDD PIC12(L)F1571 Pin Diagram – 8-Pin PDIP, SOIC, DFN, MSOP, UDFN 8 VSS 7 RA0/ICSPDAT 6 RA1/ICSPCLK 5 RA2 Note: See Table 1 for location of all peripheral functions.
PIC12(L)F1571/2 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13 3.0 Memory Organization ..............................................................................
PIC12(L)F1571/2 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
PIC12(L)F1571/2 NOTES: DS40001723D-page 6 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 1.0 DEVICE OVERVIEW 1.1 The PIC12(L)F1571/2 devices are described within this data sheet. The block diagram of these devices is shown in Figure 1-1, the available peripherals are shown in Table 1-1 and the pinout descriptions are shown in Table 1-2.
PIC12(L)F1571/2 1.1.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral, thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN. Long bit names are useful in both C and assembly programs. For example, in C, the COG1CON0 enable bit can be set with the G1EN = 1 instruction.
PIC12(L)F1571/2 FIGURE 1-1: PIC12(L)F1571/2 BLOCK DIAGRAM Rev. 10-000039E 9/12/2013 Program Flash Memory RAM PORTA CLKOUT Timing Generation CPU CLKIN INTRC Oscillator (Note 3) MCLR TMR2 TMR1 CWG1 Note 1: 2: 3: 4: TMR0 C1 Temp Indicator ADC 10-bit PWM3 DAC PWM2 FVR PWM1 EUSART(4) See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. See Figure 2-1. PIC12(L)F1572 only. 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 TABLE 1-2: PIC12(L)F1571/2 PINOUT DESCRIPTION Name RA0/AN0/C1IN+/DACOUT/ TX(2)/CK(2)/CWG1B/PWM2/ ICSPDAT/ICDDAT Function Input Type Output Type RA0 General purpose I/O. AN0 ADC channel input. C1IN+ Comparator positive input. DACOUT TX Digital-to-Analog Converter output. (3) (4) CK CWG complementary output. PWM2 PWM output. ICSPDAT ICSP™ data I/O. ICDDAT In-circuit debug data. RA1 General purpose I/O. AN1 ADC channel input. VREF+ ADC Voltage Reference input.
PIC12(L)F1571/2 TABLE 1-2: PIC12(L)F1571/2 PINOUT DESCRIPTION (CONTINUED) Name RA5/T1CKI/RX(1,2)/DT(1,2)/ CWG1A(1)/PWM1(1)/CLKIN Function Input Type Output Type General purpose I/O. RA5 T1CKI Timer1 clock input. RX DT Description USART asynchronous input. (3) (4) CWG1A USART synchronous data. CWG complementary output. PWM1 PWM output. CLKIN External Clock input (EC mode). VDD VDD Power — Positive supply. VSS VSS Power — Ground reference.
PIC12(L)F1571/2 NOTES: DS40001723D-page 12 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 2.0 ENHANCED MID-RANGE CPU • • • • This family of devices contains an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.
PIC12(L)F1571/2 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving”, for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have a hardware stack memory, 15 bits wide and 16 words deep.
PIC12(L)F1571/2 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory: - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory: - Core Registers - Special Function Registers - General Purpose RAM - Common RAM • PCL and PCLATH • Stack • Indirect Addressing Program Memory Organization The enhanced mid-range core has a 15-bit Program Counter (PC) capable of addressing a 32K x 14 program memory space.
PIC12(L)F1571/2 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC12(L)F1571 FIGURE 3-2: PROGRAM MEMORY MAP AND STACK FOR PIC12(L)F1572 Rev. 10-000040C 7/30/2013 Rev.
PIC12(L)F1571/2 3.2.1 READING PROGRAM MEMORY AS DATA 3.2.1.2 Indirect Read with FSR The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1. The program memory can be accessed as data by setting bit 7 of the FSRnH register and reading the matching INDFn register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register.
PIC12(L)F1571/2 3.3 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): • • • • 12 Core Registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of Common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’.
PIC12(L)F1571/2 3.3.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • The arithmetic status of the ALU • The Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC12(L)F1571/2 3.3.2 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses: x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.3.
2013-2015 Microchip Technology Inc.
PIC12(L)F1572 MEMORY MAP, BANK 0-7 BANK 0 000h BANK 1 080h Core Registers (Table 3-2) 00Bh BANK 2 100h Core Registers (Table 3-2) 08Bh BANK 3 180h Core Registers (Table 3-2) 10Bh BANK 4 200h Core Registers (Table 3-2) 18Bh BANK 5 280h Core Registers (Table 3-2) 20Bh BANK 6 300h Core Registers (Table 3-2) 28Bh BANK 7 380h Core Registers (Table 3-2) 30Bh Core Registers (Table 3-2) 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA 0
2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 MEMORY MAP, BANK 24-31 BANK 24 C00h BANK 25 Core Registers (Table 3-2) C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h — — — — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Unimplemented Read as ‘0’ 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 TABLE 3-7: PIC12(L)F1571/2 MEMORY MAP, BANK 27 TABLE 3-8: PIC12(L)F1571/2 MEMORY MAP, BANK 31 Bank 31 D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h DA1h DA2h DA3h DA4h DA5h DA6h DA7h DA8h DA9h DAAh DABh DACh DADh DAEh DAFh DB0h DB1h DB2h DB3h DB4h DB5h DB6h DB7h DB8h DB9h DBAh DBBh DBCh DBDh DBEh DBFh DC0h — — PWMEN PWMLD PWMOUT PWM1PHL PWM1PHH PWM1DCL PWM1DCH PWM1PRL PWM1PRH PWM1OFL PWM1OFH PWM1TMRL PWM1TMRH PWM1CON PWM1INTE PW
PIC12(L)F1571/2 3.3.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-9 can be addressed from any bank.
PIC12(L)F1571/2 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 — — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on All Other Resets Bank 0 00Ch PORTA RA<5:0> --xx xxxx --xx xxxx 00Dh — Unimplemented — — 00Eh — Unimplemented — — 00Fh — Unimplemented — — 010h — Unimplemented — — 011h PIR1 TMR1GIF 012h PIR2 — — 013h PIR3 — PWM3IF 014h — RCIF(2) ADIF TXIF(2) — — TMR2IF TMR1IF 0000 --00 0000 --00 C1IF — — — — — -
PIC12(L)F1571/2 TABLE 3-10: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 — — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on All Other Resets Bank 2 10Ch LATA LATA<5:4> — LATA<2:0> --xx -xxx --uu -uuu 10Dh — Unimplemented — — 10Eh — Unimplemented — — 10Fh — Unimplemented — — 110h — Unimplemented — — 111h CM1CON0 112h CM1CON1 C1ON C1OUT C1INTP C1INTN C1OE C1POL — C1PCH<1:0> C1SP — C1HYS C1SYNC C1NCH<2:0> 0000 -100
PIC12(L)F1571/2 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 — — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on All Other Resets Bank 4 20Ch WPUA WPUA<5:0> --11 1111 --11 1111 20Dh — Unimplemented — — 20Eh to 21Fh — Unimplemented — — Bank 5 28Ch ODCONA 28Dh to 29Fh — — — ODA<5:4> — ODA<2:0> Unimplemented --11 -111 --11 -111 — — Bank 6 30Ch SLRCONA 30Dh to 31Fh — — — SLRA<5:4> — SLRA<2:0> Unimplemented --11 -
PIC12(L)F1571/2 TABLE 3-10: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on All Other Resets Bank 10 50Ch to 51Fh — Unimplemented — — — Unimplemented — — — Unimplemented — — — Unimplemented — — Bank 11 58Ch to 59Fh Bank 12 60Ch to 61Fh Bank 13 68Ch to 690h 691h CWG1DBR — — CWG1DBR<5:0> 692h CWG1DBF — — CWG1DBF<5:0> 693h CWG1CON0 G1EN G1OEB 694h CWG1CON1 695h CWG1CON2 696h to 69F
PIC12(L)F1571/2 TABLE 3-10: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on All Other Resets Bank 27 D8Ch — Unimplemented — — D8Dh — Unimplemented — — D8Eh PWMEN — — — — — D8Fh PWMLD — — — — — PWM3LDA_A PWM2LDA_A PWM1LDA_A ---- -000 ---- -000 D90h PWMOUT — — — — — PWM3OUT_A PWM2OUT_A PWM1OUT_A ---- -000 ---- -000 D91h PWM1PHL PH<7:0> xxxx xxxx uuuu uuuu D92h PWM1PHH PH<15:8>
PIC12(L)F1571/2 TABLE 3-10: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 — — Bit 1 Bit 0 Value on POR, BOR Value on All Other Resets Bank 27 (Continued) DB0h PWM2OFCON DB1h PWM3PHL — PWM2OFM<1:0> PWM2OFO PH<7:0> xxxx xxxx uuuu uuuu DB2h PWM3PHH PH<15:8> xxxx xxxx uuuu uuuu DB3h PWM3DCL DC<7:0> xxxx xxxx uuuu uuuu DB4h PWM3DCH DC<15:8> xxxx xxxx uuuu uuuu DB5h PWM3PRL PR<7:0> xxxx xxxx uuuu uuuu DB6h PWM3PRH PR<15:8> xx
PIC12(L)F1571/2 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on All Other Resets — — Bank 31 F8Ch — FE3h — FE4h STATUS_ SHAD FE5h WREG_ SHAD FE6h BSR_ PCLATH_ SHAD FE8h FSR0L_ SHAD FE9h FSR0H_ SHAD FEAh FSR1L_ SHAD FEBh FSR1H_ SHAD FECh — FEDh STKPTR FEEh TOSL FEFh TOSH Legend: Note 1: 2: 3: — — — — — Z_SHAD Working Register Shadow — SHAD FE7h Unimplemented — — DC_
PIC12(L)F1571/2 3.4 PCL and PCLATH 3.4.2 The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC. FIGURE 3-4: LOADING OF PC IN DIFFERENT SITUATIONS Rev.
PIC12(L)F1571/2 3.5 Stack 3.5.1 All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-5 through 3-8). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.
PIC12(L)F1571/2 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 Rev. 10-000043B 7/30/2013 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL FIGURE 3-7: Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 Rev.
PIC12(L)F1571/2 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 Rev. 10-000043D 7/30/2013 TOSH:TOSL 3.5.
PIC12(L)F1571/2 FIGURE 3-9: INDIRECT ADDRESSING Rev. 10-000044A 7/30/2013 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x0FFF Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved FSR Address Range 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS40001723D-page 38 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 3.6.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address, 0x000, to FSR address, 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Rev.
PIC12(L)F1571/2 3.6.2 LINEAR DATA MEMORY The linear data memory is the region from FSR address, 0x2000, to FSR address, 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC12(L)F1571/2 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, code protection and Device ID. 4.1 Configuration Words Note: The DEBUG bit in the Configuration Words is managed automatically by device development tools, including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. There are several Configuration Word bits that allow different oscillator and memory protection options.
PIC12(L)F1571/2 4.
PIC12(L)F1571/2 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 (1) LVP R/P-1 DEBUG R/P-1 (2) LPBOREN R/P-1 (3) BORV R/P-1 R/P-1 STVREN PLLEN bit 13 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after bulk erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = On – Low-voltage programming is en
PIC12(L)F1571/2 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in the Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s.
PIC12(L)F1571/2 4.7 Register Definitions: Device ID DEVICEID: DEVICE ID REGISTER(1) REGISTER 4-3: R R R R R R DEV<13:8> bit 13 R R bit 8 R R R R R R DEV<7:0> bit 7 bit 0 Legend: R = Readable bit ‘0’ = Bit is cleared bit 13-0 x = Bit is unknown ‘1’ = Bit is set DEV<13:0>: Device ID bits Refer to Table 4-1 to determine what these bits will read on which device. A value of 3FFFh is invalid. Note 1: This location cannot be written.
PIC12(L)F1571/2 NOTES: DS40001723D-page 46 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 5.0 OSCILLATOR MODULE The oscillator module can be configured in one of the following clock modes: 5.1 Overview 1. The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications, while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module.
PIC12(L)F1571/2 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 5-1: Rev. 10-000155A 10/11/2013 FOSC<1:0> 01 Reserved 2 CLKIN 0 INTOSC PLLEN FOSC(1) 00 1 4x PLL(2) Sleep to CPU and Peripherals 1x SPLLEN 2 16 MHz SCS<1:0> 8 MHz 4 MHz 500 kHz Oscillator MFINTOSC(1) 2 MHz Prescaler HFPLL 16 MHz HFINTOSC(1) 1 MHz *500 kHz *250 kHz *125 kHz 62.5 kHz *31.
PIC12(L)F1571/2 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Internal clock sources are contained within the oscillator module.
PIC12(L)F1571/2 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<1:0> bits in the Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run time. See Section 5.
PIC12(L)F1571/2 5.2.2.3 Internal Oscillator Frequency Adjustment The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 5-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator, a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number.
PIC12(L)F1571/2 5.2.2.7 32 MHz Internal Oscillator Frequency Selection The internal oscillator block can be used with the 4x PLL associated with the external oscillator block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source: • The FOSCx bits in the Configuration Words must be set to use the INTOSC source as the device system clock (FOSC<1:0> = 00).
PIC12(L)F1571/2 FIGURE 5-3: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ MFINTOSC LFINTOSC (WDT disabled) HFINTOSC/ MFINTOSC Oscillator Delay(1) 2-Cycle Sync Running LFINTOSC 0 IRCF<3:0> =0 System Clock LFINTOSC (WDT enabled) HFINTOSC/ MFINTOSC HFINTOSC/ MFINTOSC 2-Cycle Sync Running LFINTOSC 0 IRCF <3:0> =0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Turns Off unless WDT is Enabled LFINTOSC Oscillator Delay(1) HFINTOSC/ MFINTOSC IRCF <3:0> =0 2-Cycle Sync Running 0 Syste
PIC12(L)F1571/2 5.3 Clock Switching 5.4 The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCSx) bits of the OSCCON register. The following clock sources can be selected using the SCSx bits: When clock switching from an old clock to a new clock is requested, just prior to entering Sleep mode, it is necessary to confirm that the switch is complete before the SLEEP instruction is executed.
PIC12(L)F1571/2 5.
PIC12(L)F1571/2 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER U-0 R-0/q R-q/q R-0/q R-0/q R-q/q R-0/q R-0/q — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit q = Conditional bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘0’ bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready
PIC12(L)F1571/2 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 100000 = Minimum frequency • • • 111111 = 000000 = Osci
PIC12(L)F1571/2 NOTES: DS40001723D-page 58 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 6.0 RESETS There are multiple ways to reset this device: • • • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit FIGURE 6-1: To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1.
PIC12(L)F1571/2 6.1 Power-on Reset (POR) 6.2 Brown-out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC12(L)F1571/2 6.2.1 BOR IS ALWAYS ON BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. When the BORENx bits of the Configuration Words are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. 6.2.3 When the BORENx bits of the Configuration Words are programmed to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register.
PIC12(L)F1571/2 6.
PIC12(L)F1571/2 6.4 Low-Power Brown-out Reset (LPBOR) The Low-Power Brown-out Reset (LPBOR) operates like the BOR to detect low-voltage conditions on the VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The BOR bit in PCON is used for both BOR and the LPBOR. Refer to Register 6-2.
PIC12(L)F1571/2 FIGURE 6-3: RESET START-UP SEQUENCE Rev. 10-000032A 7/30/2013 VDD Internal POR TPWRT Power-up Timer MCLR Internal RESET Int. Oscillator FOSC Begin Execution code execution (1) Internal Oscillator, PWRTEN = 0 code execution (1) Internal Oscillator, PWRTEN = 1 VDD Internal POR TPWRT Power-up Timer MCLR Internal RESET Ext.
PIC12(L)F1571/2 6.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers.
PIC12(L)F1571/2 6.13 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) RESET Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 6-2. 6.
PIC12(L)F1571/2 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 62 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 66 STATUS — — — TO PD Z DC WDTCON — — WDTPS<4:0> C 19 SWDTEN 89 Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
PIC12(L)F1571/2 NOTES: DS40001723D-page 68 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 7.0 INTERRUPTS Many peripherals produce interrupts. Refer to the corresponding chapters for details. The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. A block diagram of the interrupt logic is shown in Figure 7-1.
PIC12(L)F1571/2 7.1 Operation Interrupts are disabled upon any device Reset.
PIC12(L)F1571/2 FIGURE 7-2: INTERRUPT LATENCY Fosc Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1-Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(00
PIC12(L)F1571/2 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC CLKOUT (3) INT Pin (1) (1) INTF Interrupt Latency(2) (4) GIE INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Executed Inst (PC – 1) Inst (PC) Forced NOP Forced NOP Inst (0004h) Note 1: 2: 3: 4: INTF flag is sampled here (every Q1).
PIC12(L)F1571/2 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC12(L)F1571/2 7.
PIC12(L)F1571/2 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acquisit
PIC12(L)F1571/2 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 U-0 R/W-0/0 U-0 U-0 U-0 U-0 U-0 — — C1IE — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disa
PIC12(L)F1571/2 REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 — PWM3IE PWM2IE PWM1IE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘0’ bit 6 PWM3IE: PWM3 Interrupt Enable bit 1 = Enables the PWM3 interrupt 0 = Di
PIC12(L)F1571/2 REGISTER 7-5: R/W-0/0 PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 TMR1GIF R-0/0 ADIF RCIF (1) R/W-0/0 TXIF (1) U-0 U-0 R/W-0/0 R/W-0/0 — — TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt
PIC12(L)F1571/2 REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 U-0 U-0 R/W-0/0 U-0 U-0 U-0 U-0 U-0 — — C1IF — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5 C1IF: Numerically Controlled Oscillator Flag bit 1 = Interrupt is pending 0 = Interrupt
PIC12(L)F1571/2 REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 U-0 R-0/0 R-0/0 R-0/0 U-0 U-0 U-0 U-0 — PWM3IF(1) PWM2IF(1) PWM1IF(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘0’ bit 6 PWM3IF: PWM3 Interrupt Flag bit(1) 1 = Interrupt is pending 0 = Int
PIC12(L)F1571/2 TABLE 7-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75 — C1IE — — — — — 76 — — — — 77 — — TMR2IF TMR1IF 78 — — — — 79 — — — — 80 PIE1 TMR1GIE PIE2 — PIE3 — PWM3IE PWM2IE PWM1IE PIR1 TMR1GIF ADIF RCIF(1) PIR2 — —
PIC12(L)F1571/2 NOTES: DS40001723D-page 82 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 8.0 POWER-DOWN MODE (SLEEP) The Power-Down mode is entered by executing a SLEEP instruction. Upon entering Sleep mode, the following conditions exist: 1. WDT will be cleared but keeps running if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep.
PIC12(L)F1571/2 FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) TOST(3) CLKOUT(2) Interrupt Flag Interrupt Latency (4) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 8.
PIC12(L)F1571/2 8.
PIC12(L)F1571/2 NOTES: DS40001723D-page 86 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 9.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC12(L)F1571/2 9.1 Independent Clock Source 9.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 26.0 “Electrical Specifications” for the LFINTOSC tolerances. 9.2 The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in the Configuration Words. See Table 9-1. 9.2.
PIC12(L)F1571/2 9.
PIC12(L)F1571/2 TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 Bit 6 Bit 5 Bit 4 OSCCON SPLLEN PCON STKOVF STKUNF — RWDT STATUS — — — TO WDTCON — — Bit 3 IRCF<3:0> Bit 2 Bit 1 — Bit 0 SCS<1:0> RMCLR RI POR PD Z DC WDTPS<4:0> Register on Page 55 BOR 66 C 19 SWDTEN 89 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
PIC12(L)F1571/2 10.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs).
PIC12(L)F1571/2 See Table 10-1 for erase row size and the number of write latches for Flash program memory. TABLE 10-1: FLASH MEMORY ORGANIZATION BY DEVICE Device PIC12(L)F1571 PIC12(L)F1572 10.2.1 Row Erase (words) Write Latches (words) 16 16 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit, RD, of the PMCON1 register.
PIC12(L)F1571/2 FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC – 1) Executed Here PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD Executed Here PC +3 PC+3 PMDATH,PMDATL INSTR(PC + 1) Instruction Ignored, Forced NOP Executed Here PC + 5 PC + 4 INSTR (PC + 3) INSTR(PC + 2) Instruction Ignored, Forced NOP Executed Here INSTR (PC + 4) INSTR(PC + 3) Executed Here INS
PIC12(L)F1571/2 10.2.2 FLASH MEMORY UNLOCK SEQUENCE The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing.
PIC12(L)F1571/2 10.2.3 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit, WR, of the PMCON1 register to begin the erase operation.
PIC12(L)F1571/2 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2.
PIC12(L)F1571/2 10.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat Steps 1 through 3 until all data is written. Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time.
7 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES 6 0 7 4 PMADRH - rA r9 r8 r7 r6 3 0 7 PMADRL r5 r4 r3 r2 r1 r0 c3 c2 c1 - 5 - 0 7 PMDATH PMDATL 6 c0 Rev. 10-000004B 7/25/2013 0 8 14 11 Program Memory Write Latches 4 14 Write Latch #0 00h 14 14 14 Write Latch #14 0Eh Write Latch #1 01h Write Latch #15 0Fh PMADRL<3:0> 14 CFGS = 0 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config.
PIC12(L)F1571/2 EXAMPLE 10-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 32 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the Least Significant bits = 00000) is loaded in ADDRH:ADDRL 4.
PIC12(L)F1571/2 10.3 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC12(L)F1571/2 10.4 User ID, Device ID and Configuration Word Access When read access is initiated on an address outside the parameters listed in Table 10-2, the PMDATH:PMDATL register pair is cleared, reading back ‘0’s. Instead of accessing program memory, the User IDs, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible.
PIC12(L)F1571/2 10.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 10-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Rev. 10-000051A 7/30/2013 Start Verify Operation This routine assumes that the last row of data written was from an image saved on RAM.
PIC12(L)F1571/2 10.
PIC12(L)F1571/2 REGISTER 10-3: R/W-0/0 PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 PMADR<7:0>: Specifies Least Significant bits for Program Memory Address bits REGISTER 10-4: U-1 PMADRH: PR
PIC12(L)F1571/2 REGISTER 10-5: U-1 PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER R/W-0/0 (1) — CFGS R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) (3) LWLO FREE WRERR R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Hardware Clearable bit bit 7 Unimplemented: Read as ‘1’(1) bit
PIC12(L)F1571/2 REGISTER 10-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can only be set x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before
PIC12(L)F1571/2 NOTES: DS40001723D-page 108 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 11.0 I/O PORTS Each port has three standard registers for its operation. These registers are: • TRISx registers (Data Direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (Output Latch) • INLVLx (Input Level Control) • ODCONx registers (Open-Drain Control) • SLRCONx registers (Slew Rate Control) Ports that support analog inputs have an associated ANSELx register. When an ANSELx bit is set, the digital input buffer associated with that bit is disabled.
PIC12(L)F1571/2 11.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 11-1. For this device family, the following functions can be moved between different pins. • • • • • • These bits have no effect on the values of any TRISx register. PORTx and TRISx overrides will be routed to the correct pin. The unselected pin will be unaffected.
PIC12(L)F1571/2 11.3 11.3.1 PORTA Registers DATA REGISTER PORTA is a 6-bit wide, bidirectional port. The corresponding Data Direction register is TRISA (Register 11-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).
PIC12(L)F1571/2 11.3.7 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 11-2.
PIC12(L)F1571/2 11.
PIC12(L)F1571/2 REGISTER 11-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 — — R/W-x/u R/W-x/u U-0 LATA<5:4>(1) R/W-x/u R/W-x/u R/W-x/u LATA<2:0>(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemented: Read
PIC12(L)F1571/2 REGISTER 11-6: U-0 WPUA: WEAK PULL-UP PORTA REGISTER U-0 — R/W-1/1 R/W-1/1 R/W-1/1 — R/W-1/1 WPUA<5:0> R/W-1/1 R/W-1/1 (1,2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(1,2,3) 1 = Pull-up is enabled 0 = Pull-up
PIC12(L)F1571/2 REGISTER 11-8: SLRCONA: PORTA SLEW RATE CONTROL REGISTER U-0 U-0 — — R/W-1/1 R/W-1/1 U-0 SLRA<5:4> R/W-1/1 — R/W-1/1 R/W-1/1 SLRA<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 SLRA<5:4>: PORTA Slew Rate Enable bits For RA<5:4> Pins, Respectively
PIC12(L)F1571/2 TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name ANSELA APFCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — — ANSA4 — RXDTSEL CWGASEL CWGBSEL — Bit 2 Bit 1 Bit 0 ANSA<2:0> T1GSEL TXCKSEL P2SEL Register on Page 114 P1SEL INLVLA<5:0> 110 INLVLA — — LATA — — LATA<5:4> — LATA<2:0> 114 ODCONA — — ODA<5:4> — ODA<2:0> 115 PS<2:0> 157 WPUEN INTEDG PORTA — — SLRCONA — — SLRA<5:4> — SLRA<2:0> 116 TRISA — — TRISA<5:4> —(1) TRISA<2:0> 113 WP
PIC12(L)F1571/2 NOTES: DS40001723D-page 118 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 12.0 INTERRUPT-ON-CHANGE The PORTA and PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual port pin, or combination of port pins, can be configured to generate an interrupt.
PIC12(L)F1571/2 FIGURE 12-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) Rev. 10-000 037A 6/2/201 4 IOCANx D Q R Q4Q1 edge detect RAx IOCAPx D data bus = 0 or 1 Q D S to data bus IOCAFx Q write IOCAFx R IOCIE Q2 IOC interrupt to CPU core from all other IOCnFx individual pin detectors FOSC Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q4 Q4Q1 Q1 Q3 Q4 Q4Q1 DS40001723D-page 120 Q4 Q4Q1 Q4Q1 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 12.
PIC12(L)F1571/2 REGISTER 12-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 — — R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCAF<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAF<5:0>: Interrupt-On-Cha
PIC12(L)F1571/2 13.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with a nominal output level (VFVR) of 1.024V. The output of the FVR can be configured to supply a reference voltage to the following: • ADC input channel • Comparator positive input • Comparator negative input The FVR can be enabled by setting the FVREN bit of the FVRCON register. 13.
PIC12(L)F1571/2 TABLE 13-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral HFINTOSC BOR LDO Conditions Description FOSC<2:0> = 010 and IRCF<3:0> = 000x INTOSC is active and device is not in Sleep. BOREN<1:0> = 11 BOR is always enabled. BOREN<1:0> = 10 and BORFS = 1 BOR is disabled in Sleep mode, BOR Fast Start is enabled. BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start is enabled.
PIC12(L)F1571/2 13.
PIC12(L)F1571/2 NOTES: DS40001723D-page 126 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 14.0 TEMPERATURE INDICATOR MODULE FIGURE 14-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. Rev.
PIC12(L)F1571/2 TABLE 14-2: Name FVRCON SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on Page 118 Legend: Shaded cells are unused by the temperature indicator module. DS40001723D-page 128 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 15.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC voltage reference is software selectable to be either internally generated or externally supplied. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC12(L)F1571/2 15.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 15.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRISx and ANSELx bits. Refer to Section 11.
PIC12(L)F1571/2 TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) ADC Clock Source Device Frequency (FOSC) ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns 125 ns 250 ns 500 ns 2.0 s Fosc/4 100 200 ns 250 ns 500 ns 1.0 s 4.0 s Fosc/8 001 400 ns 500 ns 1.0 s 2.0 s 8.0 s Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s 32.0 s Fosc/64 110 3.2 s 4.0 s 8.0 s 16.
PIC12(L)F1571/2 15.1.5 INTERRUPTS 15.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC12(L)F1571/2 15.2 15.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 15.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 15.2.6 “ADC Conversion Procedure”.
PIC12(L)F1571/2 15.2.6 ADC CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC12(L)F1571/2 15.
PIC12(L)F1571/2 REGISTER 15-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 — — R/W-0/0 bit 7 R/W-0/0 ADPREF<1:0> bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 ADFM: ADC Result Format Select bit 1 = Right justified; six Most Significant bits of ADRESH are set to ‘0’ when
PIC12(L)F1571/2 REGISTER 15-3: R/W-0/0 ADCON2: ADC CONTROL REGISTER 2 R/W-0/0 R/W-0/0 TRIGSEL<3:0> R/W-0/0 (1) U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-4 TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1) 0000 = No auto-conversion trigger selected 0001 = PWM1 – PWM1_inte
PIC12(L)F1571/2 REGISTER 15-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result.
PIC12(L)F1571/2 REGISTER 15-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-2 Reserved: Do not use bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of
PIC12(L)F1571/2 15.4 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the Charge Holding Capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 15-5. The Source Impedance (RS) and the internal Sampling Switch Impedance (RSS) directly affect the time required to charge the capacitor, CHOLD. The Sampling Switch Impedance (RSS) varies over the device voltage (VDD); refer to Figure 15-5.
PIC12(L)F1571/2 FIGURE 15-5: ANALOG INPUT MODEL Rev. 10-000070B 8/5/2014 VDD RS Analog Input pin VT § 0.6V RIC 1K Sampling switch SS RSS ILEAKAGE(1) VA Legend: CHOLD CPIN ILEAKAGE RIC RSS SS VT Note 1: FIGURE 15-6: CPIN 5pF CHOLD = 12.5 pF VT § 0.
PIC12(L)F1571/2 TABLE 15-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 — ADCON1 ADFM ADCON2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> ADCS<2:0> TRIGSEL<3:0> Bit 1 Bit 0 Register on Page GO/DONE ADON 135 — — ADPREF<1:0> 136 — — — 137 — ADRESH ADC Result Register High 138, 139 ADRESL ADC Result Register Low 138, 139 ANSELA — — — ANSA4 — INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF ANSA<2:0> INTF IOCIF 114 (2) (2) 74 PIE1 TMR1GIE ADIE RCIE TXIE
PIC12(L)F1571/2 16.0 5-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The output of the DAC (DACx_output) can be selected as a reference voltage to the following: The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels.
PIC12(L)F1571/2 16.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACxCON1 register. The DAC output voltage can be determined by using Equation 16-1. 16.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value.
PIC12(L)F1571/2 16.
PIC12(L)F1571/2 NOTES: DS40001723D-page 146 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 17.0 COMPARATOR MODULE 17.1 Comparator Overview Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
PIC12(L)F1571/2 FIGURE 17-2: SINGLE COMPARATOR 17.2.2 VIN+ + VIN- – Configuring the CxPCH<1:0> bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: Output VINVIN+ 17.2 CxIN+ analog pin DAC1_output FVR_buffer2 VSS See Section 13.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section 16.
PIC12(L)F1571/2 17.2.5 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 17-2 shows the output state versus input conditions, including polarity control. TABLE 17-2: COMPARATOR OUTPUT STATE VS.
PIC12(L)F1571/2 17.4 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. See Section 26.0 “Electrical Specifications” for more information. 17.5 Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 19.
PIC12(L)F1571/2 17.
PIC12(L)F1571/2 REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 CxPCH<1:0> U-0 R/W-0/0 R/W-0/0 R/W-0/0 CxNCH<2:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bit 1 = The CxIF interrupt fl
PIC12(L)F1571/2 TABLE 17-3: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — — ANSA4 — C1OE C1POL — Bit 2 C1ON C1OUT CM1CON1 C1NTP C1INTN — — — — DACEN — DACOE — DACPSS<1:0> CDAFVR<1:0> CMOUT DAC1CON0 — — — FVRCON FVREN FVRRDY TSEN TSRNG INTCON DAC1CON1 C1SP — — Bit 0 ANSA<2:0> CM1CON0 C1PCH<1:0> Bit 1 114 C1HYS C1SYNC C1NCH<2:0> — Register on Page 151 152 — MC1OUT 152 — — 145 DACR<4:0> 145 ADFVR<1
PIC12(L)F1571/2 NOTES: DS40001723D-page 154 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 18.0 TIMER0 MODULE 18.1.2 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. • • • • • • In 8-Bit Counter mode, the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘1’.
PIC12(L)F1571/2 18.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module, ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC12(L)F1571/2 18.
PIC12(L)F1571/2 NOTES: DS40001723D-page 158 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 19.
PIC12(L)F1571/2 19.1 Timer1 Operation 19.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.
PIC12(L)F1571/2 19.3 Timer1 Prescaler Timer1 has four prescaler options, allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPSx bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 19.4 Timer1 Operation in Asynchronous Counter Mode If control bit, T1SYNC, of the T1CON register is set, the external clock input is not synchronized.
PIC12(L)F1571/2 19.5.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 19.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 19.5.
PIC12(L)F1571/2 19.6 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: 19.
PIC12(L)F1571/2 FIGURE 19-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL N Timer1 FIGURE 19-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 DS40001723D-page 164 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 FIGURE 19-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ DONE Cleared by Hardware on Falling Edge of T1GVAL Set by Software Counting Enabled on Rising Edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N Cleared by Software 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 FIGURE 19-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ DONE Cleared by Hardware on Falling Edge of T1GVAL Set by Software Counting Enabled on Rising Edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS40001723D-page 166 N Cleared by Software N+1 N+2 N+3 N+4 Set by Hardware on Falling Edge of T1GVAL Cleared by Software 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 19.
PIC12(L)F1571/2 REGISTER 19-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u bit 7 R/W-0/u T1GSS<1:0> bit 0 Legend: R = Readable bit W = Writable bit HC = Hardware Clearable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1O
PIC12(L)F1571/2 TABLE 19-5: Name ANSELA APFCON INTCON OSCSTAT SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 — — — ANSA4 — — T1GSEL RXDTSEL CWGASEL CWGBSEL Bit 3 Bit 2 Bit 1 Bit 0 ANSA<2:0> TXCKSEL P2SEL Register on Page 114 P1SEL 110 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 56 (2) (2) PIE1 TMR1GIE ADIE RCIE TXIE — — TMR2IE TMR1IE 75 PIR1 TMR1GIF ADIF RCIF(2) TXIF(2) — — TMR2
PIC12(L)F1571/2 NOTES: DS40001723D-page 170 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 20.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-Bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16 and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2 See Figure 20-1 for a block diagram of Timer2. FIGURE 20-1: TIMER2 BLOCK DIAGRAM Rev.
PIC12(L)F1571/2 20.1 Timer2 Operation The clock input to the Timer2 module is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle.
PIC12(L)F1571/2 20.
PIC12(L)F1571/2 NOTES: DS40001723D-page 174 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 21.
PIC12(L)F1571/2 FIGURE 21-2: EUSART RECEIVE BLOCK DIAGRAM Rev.
PIC12(L)F1571/2 21.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard Non-Return-to-Zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC12(L)F1571/2 21.1.1.5 TSR Status 21.1.1.7 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 1. 2. 3.
PIC12(L)F1571/2 TABLE 21-1: Name BAUDCON INTCON PIE1 PIR1 RCSTA SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 186 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75 TMR1GIF ADIF (1) RCIF TXIF (1) — — TMR2IF TMR1IF 78 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185* SPBRGL BRG<7:0> 187* SP
PIC12(L)F1571/2 21.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 21-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC12(L)F1571/2 21.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
PIC12(L)F1571/2 21.1.2.8 Asynchronous Reception Setup 21.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 21.4 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSELx bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register, and the GIE and PEIE bits of the INTCON register.
PIC12(L)F1571/2 TABLE 21-2: Name BAUDCON INTCON PIE1 PIR1 SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 186 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75 ADIF (1) (1) — — TMR2IF TMR1IF TMR1GIF RCIF RCREG TXIF EUSART Receive Data Register RCSTA SPEN RX9 SREN CREN SPBRGL FERR OERR RX9D
PIC12(L)F1571/2 21.
PIC12(L)F1571/2 REGISTER 21-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled (configures RX/DT and TX/CK
PIC12(L)F1571/2 REGISTER 21-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-ba
PIC12(L)F1571/2 21.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. The SPBRGH/SPBRGL register pair determines the period of the free-running baud rate timer.
PIC12(L)F1571/2 TABLE 21-3: BAUD RATE FORMULAS Configuration Bits SYNC BRG16 BRGH BRG/EUSART Mode Baud Rate Formula FOSC/[64 (n+1)] 0 0 0 8-bit/Asynchronous 0 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous FOSC/[16 (n+1)] FOSC/[4 (n+1)] Legend: x = Don’t care; n = value of SPBRGH/SPBRGL register pair.
PIC12(L)F1571/2 TABLE 21-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG Value (decimal) Actual Rate % Error SPBRG Value (decimal) Actual Rate % Error SPBRG Value (decimal) Actual Rate % Error SPBRG Value (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.
PIC12(L)F1571/2 TABLE 21-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG Value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG Value (decimal) FOSC = 3.6864 MHz Actual Rate % Error SPBRG Value (decimal) FOSC = 1.000 MHz Actual Rate % Error SPBRG Value (decimal) 207 300 — — — — — — — — — 300 0.16 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.
PIC12(L)F1571/2 TABLE 21-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz Actual Rate FOSC = 18.432 MHz % Error SPBRG Value (decimal) Actual Rate % Error SPBRG Value (decimal) FOSC = 16.000 MHz Actual Rate FOSC = 11.0592 MHz % Error SPBRG Value (decimal) Actual Rate % Error SPBRG Value (decimal) 300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 -0.01 4166 1200 0.
PIC12(L)F1571/2 21.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”), which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges, including the Stop bit edge.
PIC12(L)F1571/2 21.4.2 AUTO-BAUD OVERFLOW 21.4.3.1 Special Considerations During the course of Automatic Baud Detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. The overflow condition will set the RCIF flag.
PIC12(L)F1571/2 FIGURE 21-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 WUE bit Auto-Cleared Bit Set by User RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set.
PIC12(L)F1571/2 21.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted.
PIC12(L)F1571/2 21.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC12(L)F1571/2 FIGURE 21-10: SYNCHRONOUS TRANSMISSION RX/DT Pin bit 0 bit 1 bit 2 bit 7 bit 0 TX/CK Pin (SCKP = 0) bit 7 bit 1 Word 1 Word 2 TX/CK Pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: ‘1’ ‘1’ Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words. FIGURE 21-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT Pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK Pin Write to TXREG Reg.
PIC12(L)F1571/2 21.5.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC12(L)F1571/2 FIGURE 21-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT Pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK Pin (SCKP = 0) TX/CK Pin (SCKP = 1) Write to SREN bit SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC12(L)F1571/2 21.5.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the EUSART for synchronous slave operation: • • • • • 1. SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation.
PIC12(L)F1571/2 21.5.2.3 EUSART Synchronous Slave Reception 21.5.2.4 1. The operation of the Synchronous Master and Slave modes is identical (Section 21.5.1.5 “Synchronous Master Reception”), with the following exceptions: 2. 3. • Sleep • CREN bit is always set, therefore, the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC12(L)F1571/2 NOTES: DS40001723D-page 202 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 22.0 16-BIT PULSE-WIDTH MODULATION (PWM) MODULE Each PWM module has four Offset modes: • • • • The Pulse-Width Modulation (PWM) module generates a pulse-width modulated signal determined by the phase, duty cycle, period and offset event counts that are contained in the following registers: • • • • Using the Offset modes, each PWM module can offset its waveform relative to any other PWM module in the same device. For a more detailed description of the Offset modes, refer to Section 22.
PIC12(L)F1571/2 FIGURE 22-2: LOAD TRIGGER BLOCK DIAGRAM Rev. 10-000153A 4/21/2014 LD3_trigger(1) 11 (1) 10 LD1_trigger(1) 01 Reserved 00 LD2_trigger 1 0 PWMxLDS LDx_trigger 22.1 PWM_clock 1. The input corresponding to a PWM module’s own load trigger is reserved. 2. PWMxLDA is cleared by hardware upon LDx_trigger. Fundamental Operation FIGURE 22-3: The PWM module produces a 16-bit resolution pulse-width modulated output.
PIC12(L)F1571/2 22.2 PWM Modes PWM modes are selected with the MODE<1:0> bits of the PWMxCON register (Register 22-1). In all PWM modes, an offset match event can also be used to synchronize the PWMxTMR in three Offset modes. See Section 22.3 “Offset Modes” for more information. 22.2.1 STANDARD MODE The Standard mode (MODE<1:0> = 00) selects a single-phase PWM output. The PWM output in this mode is determined by when the period, duty cycle and phase counts match the PWMxTMR value.
STANDARD PWM MODE TIMING DIAGRAM Rev. 10-000142A 9/5/2013 Period Duty Cycle Phase PWMxCLK PWMxPR 10 PWMxPH 4 PWMxDC 9 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 PWMxOUT FIGURE 22-5: SET ON MATCH PWM MODE TIMING DIAGRAM Rev. 10-000143A 9/5/2013 Period Phase 2013-2015 Microchip Technology Inc.
2013-2015 Microchip Technology Inc. FIGURE 22-6: TOGGLE ON MATCH PWM MODE TIMING DIAGRAM Rev. 10-000144A 9/5/2013 Period Phase PWMxCLK PWMxPR 10 PWMxPH 4 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 PWMxOUT FIGURE 22-7: CENTER-ALIGNED PWM MODE TIMING DIAGRAM Rev. 10-000 145A Rev.
PIC12(L)F1571/2 22.3 Offset Modes The Offset modes provide the means to adjust the waveform of a slave PWM module relative to the waveform of a master PWM module in the same device. 22.3.1 INDEPENDENT RUN MODE In Independent Run mode (OFM<1:0> = 00), the PWM module is unaffected by the other PWM modules in the device. The PWMxTMR associated with the PWM module in this mode starts counting as soon as the EN bit associated with this PWM module is set and continues counting until the EN bit is cleared.
2013-2015 Microchip Technology Inc. FIGURE 22-8: INDEPENDENT RUN MODE TIMING DIAGRAM Rev.
SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM Rev. 10-000 147B 7/8/201 5 Period Duty Cycle Phase Offset PWMxCLK PWMxPR 10 PWMxPH 3 PWMxDC 5 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 PWMxOUT OFx_match PWMyTMR 0 PWMyPR 4 PWMyPH 0 PWMyDC 1 2013-2015 Microchip Technology Inc.
2013-2015 Microchip Technology Inc. FIGURE 22-10: ONE-SHOT SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM Rev.
CONTINUOUS SLAVE RUN MODE WITH IMMEDIATE RESET AND SYNC START TIMING DIAGRAM Rev. 10-000 149B 7/8/201 5 Period Duty Cycle Phase Offset PWMxCLK PWMxPR 10 PWMxPH 3 PWMxDC 5 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 1 2 3 4 0 1 2 3 4 0 1 1 2 3 4 PWMxOUT OFx_match PWMyTMR 0 PWMyPR 4 PWMyPH 1 PWMyDC 2 2013-2015 Microchip Technology Inc.
2013-2015 Microchip Technology Inc. FIGURE 22-12: OFFSET MATCH ON INCREMENTING TIMER TIMING DIAGRAM Rev.
OFFSET MATCH ON DECREMENTING TIMER TIMING DIAGRAM Rev. 10-000 151B 7/9/201 5 Period Duty Cycle Offset PWMxCLK PWMxPR 6 PWMxDC 2 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 6 5 4 3 2 1 0 0 1 2 3 0 1 2 3 4 4 3 PWMxOUT OF5_match PH5_match DC5_match PR5_match PWMyTMR 0 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 22.4 Reload Operation Four of the PWM module control register pairs and one control bit are double-buffered so that all can be updated simultaneously. These include: • • • • • PWMxPHH:PWMxPHL register pair PWMxDCH:PWMxDCL register pair PWMxPRH:PWMxPRL register pair PWMxOFH:PWMxOFL register pair OFO control bit When written to, these registers do not immediately affect the operation of the PWM.
PIC12(L)F1571/2 22.7 Register Definitions: PWM Control TABLE 22-1: Long bit name prefixes for the 16-bit PWM peripherals are shown in Table 22-1. Refer to Section 1.
PIC12(L)F1571/2 REGISTER 22-2: PWMxINTE: PWMx INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — OFIE PHIE DCIE PRIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-4 Unimplemented: Read as ‘0’ bit 3 OFIE: Offset Interrupt Enable bit 1 = Interrupts CPU on offset match 0
PIC12(L)F1571/2 REGISTER 22-3: PWMxINTF: PWMx INTERRUPT REQUEST REGISTER U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 — — — — OFIF PHIF R/W/HS-0/0 R/W/HS-0/0 DCIF bit 7 PRIF bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-4 Unimplemented: Read as ‘0’ bit 3 OFIF: Offset Interrupt Flag bit(1) 1 = Offset
PIC12(L)F1571/2 REGISTER 22-4: U-0 PWMxCLKCON: PWMx CLOCK CONTROL REGISTER R/W-0/0 — R/W-0/0 R/W-0/0 PS<2:0> U-0 U-0 — — R/W-0/0 bit 7 R/W-0/0 CS<1:0> bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘0’ bit 6-4 PS<2:0>: Clock Source Prescaler Select bits 111 = Divides clock source by 128 1
PIC12(L)F1571/2 REGISTER 22-5: PWMxLDCON: PWMx RELOAD TRIGGER SOURCE SELECT REGISTER R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 LDA(1) LDT — — — — R/W-0/0 bit 7 R/W-0/0 LDS<1:0> bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 LDA: Load Buffer Armed bit(1) If LDT = 1: 1 = Loads the OFx, PHx, DCx and PRx buffers at the end
PIC12(L)F1571/2 REGISTER 22-6: U-0 PWMxOFCON: PWMx OFFSET TRIGGER SOURCE SELECT REGISTER R/W-0/0 — R/W-0/0 R/W-0/0 U-0 U-0 OFO(1) — — OFM<1:0> R/W-0/0 R/W-0/0 OFS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘0’ bit 6-5 OFM<1:0>: Offset Mode Select bits 11 = Continuous Slav
PIC12(L)F1571/2 REGISTER 22-7: R/W-x/u PWMxPHH: PWMx PHASE COUNT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PH<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 PH<15:8>: PWMx Phase High bits Upper eight bits of PWM phase count.
PIC12(L)F1571/2 REGISTER 22-9: R/W-x/u PWMxDCH: PWMx DUTY CYCLE COUNT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DC<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 DC<15:8>: PWMx Duty Cycle High bits Upper eight bits of PWM duty cycle count.
PIC12(L)F1571/2 REGISTER 22-11: PWMxPRH: PWMx PERIOD COUNT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 PR<15:8>: PWMx Period High bits Upper eight bits of PWM period count.
PIC12(L)F1571/2 REGISTER 22-13: PWMxOFH: PWMx OFFSET COUNT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u OF<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 OF<15:8>: PWMx Offset High bits Upper eight bits of PWM offset count.
PIC12(L)F1571/2 REGISTER 22-15: PWMxTMRH: PWMx TIMER HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u TMR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 TMR<15:8>: PWMx Timer High bits Upper eight bits of PWM timer counter.
PIC12(L)F1571/2 Note: There are no long and short bit name variants for the following three mirror registers REGISTER 22-17: PWMEN: PWMEN BIT ACCESS REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — — PWM3EN_A PWM2EN_A PWM1EN_A bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-3 Unimplemented:
PIC12(L)F1571/2 TABLE 22-2: Name OSCCON SUMMARY OF REGISTERS ASSOCIATED WITH PWM Bit 7 Bit 6 Bit 5 SPLLEN Bit 4 Bit 3 Bit 2 IRCF<3:0> Bit 1 — Bit 0 SCS<1:0> Register on Page 55 PIE3 — PWM3IE PWM2IE PWM1IE — — — — PIR3 — PWM3IF PWM2IF PWM1IF — — — — 80 PWMEN — — — — — PWM3EN_A PWM2EN_A PWM1EN_A 227 PWMLD — — — — — PWM3LDA_A PWM2LDA_A PWM1LDA_A 227 PWMOUT — — — — — PWM3OUT_A PWM2OUT_A PWM1OUT_A 227 77 PWM1PHL PH<7:0> 222 PWM1PHH PH<15:8> 222
PIC12(L)F1571/2 TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH PWM (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page PWM3INTE — — — — OFIE PHIE DCIE PRIE 217 PWM3INTF — — — — OFIF PHIF DCIF PRIF PWM3CLKCON — — — — — OFO — Name PS<2:0> PWM3LDCON LDA PWM3OFCON — LDT — OFM<1:0> 218 CS<1:0> 219 — LDS<1:0> 220 — OFS<1:0> 221 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
PIC12(L)F1571/2 NOTES: DS40001723D-page 230 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 23.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band delay from a selection of input sources. 23.3 Selectable Input Sources The CWG generates the output waveforms from the input sources in Table 23-1.
SIMPLIFIED CWG BLOCK DIAGRAM Rev. 10-000123D 7/10/2015 GxASDLA 2 00 GxCS 1 FOSC 10 ‘1' 11 CWGxDBR cwg_clock GxASDLA = 01 6 HFINTOSC GxIS ‘0' C1OUT_async Reserved PWM1_out PWM2_out PWM3_out Reserved Reserved Reserved = 0 R S TRISx Q GxOEA GxPOLA Input Source CWGxDBF R 6 Q GxOEB EN = 0 R 1 GxPOLB 00 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 FIGURE 23-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN) cwg_clock PWM1 CWGxA Rising Edge Dead Band Falling Edge Dead Band Rising Edge Rising Edge Dead Band Falling Edge Dead Band Dead Band CWGxB 23.5 Dead-Band Control Dead-band control provides for non-overlapping output signals to prevent shoot-through current in power switches. The CWG contains two 6-bit dead-band counters. One dead-band counter is used for the rising edge of the input source control.
DEAD-BAND OPERATION, CWGxDBR = 01h, CWGxDBF = 02h cwg_clock Input Source CWGxA CWGxB FIGURE 23-4: DEAD-BAND OPERATION, CWGxDBR = 03h, CWGxDBF = 04h, SOURCE SHORTER THAN DEAD BAND cwg_clock Input Source CWGxA 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 23.8 Dead-Band Uncertainty 23.9 Auto-Shutdown Control When the rising and falling edges of the input source triggers the dead-band counters, the input may be asynchronous. This will create some uncertainty in the dead-band time delay. The maximum uncertainty is equal to one CWG clock period. Refer to Equation 23-1 for more detail. Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit.
PIC12(L)F1571/2 23.10 Operation During Sleep 23.11.1 The CWG module operates independently from the system clock, and will continue to run during Sleep provided that the clock and input sources selected remain active. The levels driven to the output pins, while the shutdown input is true, are controlled by the GxASDLA and GxASDLB bits of the CWGxCON1 register (Register 23-3). GxASDLA controls the CWG1A override level and GxASDLB controls the CWG1B override level.
2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 23.
PIC12(L)F1571/2 REGISTER 23-2: R/W-x/u CWGxCON1: CWGx CONTROL REGISTER 1 R/W-x/u R/W-x/u GxASDLB<1:0> R/W-x/u U-0 GxASDLA<1:0> — R/W-0/0 R/W-0/0 R/W-0/0 GxIS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 GxASDLB<1:0>: CWGx Shutdown State for CWGxB bits When an Auto-Shutdown Event is Present (GxASE =
PIC12(L)F1571/2 REGISTER 23-3: CWGxCON2: CWGx CONTROL REGISTER 2 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 U-0 GxASE GxARSEN — — — GxASDSC1 GxASDSFLT — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 GxASE: Auto-Shutdown Event Status bit 1 = An auto-shutdown event has occurred 0 = No auto-shutdown eve
PIC12(L)F1571/2 REGISTER 23-4: CWGxDBR: CWGx COMPLEMENTARY WAVEFORM GENERATOR RISING DEAD-BAND COUNT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CWGxDBR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CWGxDBR
PIC12(L)F1571/2 TABLE 23-2: Name ANSELA CWG1CON0 CWG1CON1 SUMMARY OF REGISTERS ASSOCIATED WITH CWG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 114 G1EN G1OEB — — G1CS0 238 G1ASDLB<1:0> CWG1CON2 G1ASE G1ARSEN CWG1DBF — — CWG1DBR — — TRISA — — G1OEA G1POLB G1POLA G1ASDLA<1:0> — — — — — G1IS<1:0> G1ASDSC1 G1ASDSFLT 239 — CWG1DBF<5:0> 241 CWG1DBR<5:0> TRISA<5:4> —(1) TRISA2 240 241 TRISA<1:0> 113 Legend: — =
PIC12(L)F1571/2 24.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode, the program memory, User IDs and the Configuration Words are programmed through serial communications.
PIC12(L)F1571/2 FIGURE 24-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Rev. 10-000128A 7/30/2013 Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins For additional interface recommendations, refer to your specific device programmer manual prior to PCB design.
PIC12(L)F1571/2 25.0 INSTRUCTION SET SUMMARY 25.1 Read-Modify-Write Operations • Byte-Oriented • Bit-Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified and the result is stored according to either the instruction or the destination designator, ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC12(L)F1571/2 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal)
PIC12(L)F1571/2 TABLE 25-3: ENHANCED MID-RANGE INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear
PIC12(L)F1571/2 TABLE 25-3: ENHANCED MID-RANGE INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 000
PIC12(L)F1571/2 25.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. k Operands: 0 k 255 Operation: (W) .AND.
PIC12(L)F1571/2 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC12(L)F1571/2 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The 11-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC12(L)F1571/2 DECFSZ Decrement f, Skip if 0 INCFSZ Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
PIC12(L)F1571/2 LSLF Logical Left Shift MOVF Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) f {,d} Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC12(L)F1571/2 MOVIW Move INDFn to W MOVLP Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Syntax: [ label ] MOVLP k Operands: 0 k 127 Operation: k PCLATH Status Affected: None Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Description: The 7-bit literal ‘k’ is loaded into the PCLATH register.
PIC12(L)F1571/2 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged Status Affected: None Mode Syntax Preincrem
PIC12(L)F1571/2 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Return from subroutine.
PIC12(L)F1571/2 RRF Rotate Right f through Carry SUBLW Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
PIC12(L)F1571/2 SWAPF Swap Nibbles in f XORLW Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Operation: (W) .XOR. k W) Operation: Status Affected: Z Status Affected: None Description: Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’.
PIC12(L)F1571/2 26.0 ELECTRICAL SPECIFICATIONS 26.1 Absolute Maximum Ratings(†) Ambient temperature under bias............................................................................................................ -40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on pins with respect to VSS: on VDD pin PIC12F1571/2 .................................................
PIC12(L)F1571/2 26.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC12LF1571/2 VDDMIN (FOSC 16 MHz) ............................................................................................................... +1.8V VDDMIN (FOSC 32 MHz) ...............................................................................................
PIC12(L)F1571/2 FIGURE 26-1: VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC12F1571/2 ONLY Rev. 10-000130B 9/19/2013 VDD (V) 5.5 2.5 2.3 0 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 26-7 for each Oscillator mode’s supported frequencies. FIGURE 26-2: VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC12LF1571/2 ONLY Rev. 10-000131B 9/19/2013 VDD (V) 3.6 2.5 1.
PIC12(L)F1571/2 26.3 DC Characteristics TABLE 26-1: SUPPLY VOLTAGE PIC12LF1571/2 Standard Operating Conditions (unless otherwise stated) PIC12F1571/2 Param. No. D001 Sym. VDD Characteristic Min. Typ† Max. Units VDDMIN 1.8 2.5 — — VDDMAX 3.6 3.6 V V FOSC 16 MHz FOSC 32 MHz (Note 3) 2.3 2.5 — — 5.5 5.5 V V FOSC 16 MHz FOSC 32 MHz (Note 3) 1.5 — — V Device in Sleep mode 1.7 — — V Device in Sleep mode — 1.6 — V — 1.6 — V — 0.
PIC12(L)F1571/2 FIGURE 26-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR Rearm VSS TVLOW(3) Note 1: 2: 3: TPOR(2) When NPOR is low, the device is held in Reset. TPOR: 1 s typical. TVLOW: 2.7 s typical. 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 TABLE 26-2: SUPPLY CURRENT (IDD)(1,2) PIC12LF1571/2 Standard Operating Conditions (unless otherwise stated) PIC12F1571/2 Param. No. Device Characteristics D013 D013 D014 D014 D015 D015 D016 D016 Min. Typ† Max. Units — 35 44 — 60 — Conditions VDD Note A 1.8 69 A 3.0 FOSC = 1 MHz, External Clock (ECM), Medium Power mode 68 93 A 2.3 — 91 120 A 3.0 — 131 160 A 5.0 — 116 132 A 1.8 — 203 233 A 3.0 — 174 221 A 2.
PIC12(L)F1571/2 TABLE 26-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED) PIC12LF1571/2 Standard Operating Conditions (unless otherwise stated) PIC12F1571/2 Param. No. Device Characteristics Conditions Min. Typ† Max. Units D018A* — 2 2.4 mA 3.0 FOSC = 32 MHz, HFINTOSC (Note 3) D018A* — 2.1 2.5 mA 3.0 — 2.2 2.6 mA 5.0 FOSC = 32 MHz, HFINTOSC (Note 3) D019A — 1.7 1.9 mA 3.0 FOSC = 32 MHz, External Clock (ECH), High-Power mode (Note 3) D019A — 1.8 2 mA 3.0 — 1.9 2.3 mA 5.
PIC12(L)F1571/2 TABLE 26-3: POWER-DOWN CURRENTS (IPD)(1,2) PIC12LF1571/2 Operating Conditions (unless otherwise stated) Low-Power Sleep Mode PIC12F1571/2 Low-Power Sleep Mode, VREGPM = 1 Param. No. D022 Device Characteristics Base IPD D022 Base IPD D022A Base IPD D023 D023 Conditions Min. Typ† Max. +85°C Max. +125°C Units — 0.020 0.6 2.6 A 1.8 — 0.025 0.8 2.9 A 3.0 — 0.2 0.9 2.8 A 2.3 — 0.3 3.0 3.8 A 3.0 — 0.4 3.6 4.5 A 5.0 — 9 14 15 A 2.
PIC12(L)F1571/2 TABLE 26-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED) PIC12LF1571/2 Operating Conditions (unless otherwise stated) Low-Power Sleep Mode PIC12F1571/2 Low-Power Sleep Mode, VREGPM = 1 Param. No. Conditions Min. Typ† Max. +85°C Max. +125°C Units D027 — 4 7 9 A — 4.2 8 10 A 3.0 D027 — 13 20 21 A 2.3 — 14 23 25 A 3.0 — 16 24 26 A 5.0 — 20 35 36 A 1.8 — 21 36 38 A 3.0 — 28 47 48 A 2.3 — 29 51 52 A 3.
PIC12(L)F1571/2 TABLE 26-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. VIL Characteristic Min. Typ† Max. Units — — Conditions — 0.8 V 4.5V VDD 5.5V — 0.15 VDD V 1.8V VDD 4.5V 2.0V VDD 5.5V Input Low Voltage I/O Ports: D030 with TTL Buffer D030A D031 D032 with Schmitt Trigger Buffer — — 0.2 VDD V with I2C Levels — — 0.3 VDD V with SMbus Levels — — 0.8 V — — 0.2 VDD V MCLR VIH 2.7V VDD 5.
PIC12(L)F1571/2 TABLE 26-5: MEMORY PROGRAMMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP Pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA D112 VBE VDD for Bulk Erase 2.
PIC12(L)F1571/2 TABLE 26-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. TH01 TH02 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TH03 TJMAX TH04 PD TH05 Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 56.7 C/W 8-pin DFN 3x3 mm package 89.3 C/W 8-pin PDIP package 149.5 C/W 8-pin SOIC package 39.
PIC12(L)F1571/2 26.4 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2.
PIC12(L)F1571/2 FIGURE 26-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS02 OS04 OS04 OS03 CLKOUT (CLKOUT Mode) Note 1: See Table 26-10. TABLE 26-7: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. Typ† Max. Units Conditions DC — 0.
PIC12(L)F1571/2 TABLE 26-8: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Freq. Tolerance Min. Typ† Max. Units OS08 HFOSC Internal Calibrated HFINTOSC Frequency(1) ±2% — 16.0 — MHz OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz OS10* TWARM HFINTOSC Wake-up from Sleep Start-up Time — — 5 15 s LFINTOSC Wake-up from Sleep Start-up Time — — 0.5 — ms Conditions VDD = 3.
PIC12(L)F1571/2 FIGURE 26-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 26-10: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions OS11 TosH2ckL FOSC to CLKOUT(1) — — 70 ns 3.3V VDD 5.
PIC12(L)F1571/2 FIGURE 26-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR PWRT Time-out 33 32 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) 34 31 34 I/O Pins Note 1: Asserted low. 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions 2 — — s 10 16 27 ms Oscillator Start-up Timer Period(1) — 1024 — TOSC TPWRT Power-up Timer Period 40 65 140 ms 34* TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset — — 2.0 s 35 VBOR Brown-out Reset Voltage(2) 2.55 2.
PIC12(L)F1571/2 FIGURE 26-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 26-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler With Prescaler 41* TT0L T0CKI Low Pulse Width No Prescaler With Prescaler Typ† Max. Units 0.5 TCY + 20 — — ns 10 — — ns 0.
PIC12(L)F1571/2 TABLE 26-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = +25°C Param. Sym. No. Characteristic Min. Typ† Max. AD01 NR Resolution — — 10 AD02 EIL Integral Error — ±1 ±1.7 AD03 EDL Differential Error AD04 EOFF Offset Error AD05 EGN AD06 AD07 VAIN Full-Scale Range AD08 ZAIN Recommended Impedance of Analog Voltage Source * † Note 1: 2: 3: 4: Units Conditions bit LSb VREF = 3.
PIC12(L)F1571/2 FIGURE 26-11: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 FIGURE 26-12: ADC CONVERSION TIMING (ADC CLOCK FROM FRC) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 OLD_DATA ADRES 2 1 0 NEW_DATA 1 TCY ADIF GO Sample 3 DONE AD132 Sampling Stopped Note 1: If the ADC clock source is selected
PIC12(L)F1571/2 TABLE 26-14: ADC CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Sym. No. AD130* TAD AD131 TCNV Characteristic Min. Typ† Max. Units Conditions ADC Clock Period (TADC) 1.0 — 6.0 s FOSC-based ADC Internal FRC Oscillator Period (TFRC) 1.0 2.0 6.0 s ADCS<2:0> = x11 (ADC FRC mode) Conversion Time (not including Acquisition Time)(1) — 11 — TAD Set GO/DONE bit to conversion complete s AD132* TACQ Acquisition Time — 5.
PIC12(L)F1571/2 TABLE 26-15: COMPARATOR SPECIFICATIONS(1) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = +25°C Param. No. CM01 Sym. Characteristics VIOFF Input Offset Voltage Min. Typ. Max. Units — ±7.
PIC12(L)F1571/2 FIGURE 26-13: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 26-4 for load conditions. TABLE 26-17: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. US120 US121 US122 Symbol TCKH2DTV TCKRF TDTRF FIGURE 26-14: Characteristic Min. Max. Units Conditions SYNC XMIT (Master and Slave) Clock High to Data-Out Valid — 80 ns 3.0V VDD 5.5V — 100 ns 1.
PIC12(L)F1571/2 27.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented is outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC12(L)F1571/2 FIGURE 27-1: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC12LF1571/2 ONLY 6.0 5.5 Max. Max: 85°C + 3ı Typical: 25°C 5.0 4.5 Typical IDD (µA) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC12F1571/2 ONLY FIGURE 27-2: 25 Max: 85°C + 3ı Typical: 25°C 20 Max. IDD (µA) Typical 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC12(L)F1571/2 FIGURE 27-3: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC12LF1571/2 ONLY 40 Max: 85°C + 3ı Typical: 25°C 35 Max. Typical IDD (µA) 30 25 20 15 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 27-4: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC12F1571/2 ONLY 50 Max. Max: 85°C + 3ı Typical: 25°C 45 IDD (µA) 40 Typical 35 30 25 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 FIGURE 27-5: IDD TYPICAL, EC OSCILLATOR, MEDIUM POWER MODE, PIC12LF1571/2 ONLY 300 Typical: 25°C 250 4 MHz IDD (µA) 200 150 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IDD MAXIMUM, EC OSCILLATOR, MEDIUM POWER MODE, PIC12LF1571/2 ONLY FIGURE 27-6: 300 4 MHz Max: 85°C + 3ı 250 IDD (µA) 200 150 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC12(L)F1571/2 FIGURE 27-7: IDD TYPICAL, EC OSCILLATOR, MEDIUM POWER MODE, PIC12F1571/2 ONLY 350 4 MHz Typical: 25°C 300 IDD (µA) 250 200 150 1 MHz 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 27-8: IDD MAXIMUM, EC OSCILLATOR, MEDIUM POWER MODE, PIC12F1571/2 ONLY 400 350 4 MHz Max: 85°C + 3ı 300 IDD (µA) 250 200 1 MHz 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 FIGURE 27-9: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC12LF1571/2 ONLY 2.5 Typical: 25°C IDD (mA) 2.0 32 MHz 1.5 16 MHz 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC12LF1571/2 ONLY FIGURE 27-10: 2.5 Max: 85°C + 3ı 32 MHz IDD (mA) 2.0 1.5 16 MHz 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC12(L)F1571/2 FIGURE 27-11: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC12F1571/2 ONLY 2.5 Typical: 25°C 2.0 32 MHz IDD (mA) 1.5 16 MHz 1.0 8 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 27-12: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC12F1571/2 ONLY 2.5 Max: 85°C + 3ı 32 MHz IDD (mA) 2.0 1.5 16 MHz 1.0 8 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 FIGURE 27-13: IDD, LFINTOSC, FOSC = 31 kHz, PIC12LF1571/2 ONLY 10 Max. 9 Max: 85°C + 3ı Typical: 25°C Typical IDD (µA) 8 7 6 5 4 3 2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 27-14: IDD, LFINTOSC, FOSC = 31 kHz, PIC12F1571/2 ONLY 25 Max: 85°C + 3ı Typical: 25°C 20 Max. IDD (µA) Typical 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001723D-page 290 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 FIGURE 27-15: IDD, MFINTOSC, FOSC = 500 kHz, PIC12LF1571/2 ONLY 170 160 Max: 85°C + 3ı Typical: 25°C Max. IDD (µA) 150 140 Typical 130 120 110 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 27-16: IDD, MFINTOSC, FOSC = 500 kHz, PIC12F1571/2 ONLY 260 Max. Max: 85°C + 3ı Typical: 25°C 240 Typical 220 IDD (µA) 200 180 160 140 120 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 FIGURE 27-17: IDD TYPICAL, HFINTOSC, PIC12LF1571/2 ONLY 1.4 16 MHz Typical: 25°C 1.2 IDD (mA) 1.0 8 MHz 0.8 4 MHz 0.6 2 MHz 0.4 1 MHz 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IDD MAXIMUM, HFINTOSC, PIC12LF1571/2 ONLY FIGURE 27-18: 1.4 16 MHz Max: 85°C + 3ı 1.2 1.0 IDD (mA) 8 MHz 0.8 4 MHz 2 MHz 0.6 1 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC12(L)F1571/2 FIGURE 27-19: IDD TYPICAL, HFINTOSC, PIC12F1571/2 ONLY 1.4 16 MHz Typical: 25°C 1.2 1.0 IDD (mA) 8 MHz 0.8 4 MHz 2 MHz 0.6 1 MHz 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 27-20: IDD MAXIMUM, HFINTOSC, PIC12F1571/2 ONLY 1.6 1.4 16 MHz Max: 85°C + 3ı 1.2 IDD (mA) 1.0 8 MHz 0.8 4 MHz 2 MHz 0.6 1 MHz 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 FIGURE 27-21: IPD BASE, LOW-POWER SLEEP MODE, PIC12LF1571/2 ONLY 350 300 Max: 85°C + 3ı Typical: 25°C Max. IPD (nA (nA) 250 200 150 100 Typical 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IPD BASE, LOW-POWER SLEEP MODE, PIC12F1571/2 ONLY FIGURE 27-22: 0.8 0.7 Max: 85°C + 3ı Typical: 25°C IPD (µA (µA) 0.6 Max 0.5 0.4 0.3 Typical 0.2 0.1 0.0 20 2.0 2 2.5 5 3 3.0 0 3 3.5 5 4 4.0 0 4 4.5 5 5 5.0 0 5 5.5 5 6 6.
PIC12(L)F1571/2 FIGURE 27-23: IPD, WATCHDOG TIMER (WDT), PIC12LF1571/2 ONLY 1.0 0.9 Max: 85°C + 3ı Typical: 25°C 0.8 Max. IPD (µA) 0.7 0.6 Typical 0.5 04 0.4 0.3 0.2 0.1 0.0 16 1.6 1 1.8 8 2 2.0 0 2 2.2 2 2 2.4 4 2 2.6 6 2 2.8 8 3 3.0 0 3 3.2 2 3 3.4 4 3 3.6 6 3 3.8 8 VDD (V) FIGURE 27-24: IPD, WATCHDOG TIMER (WDT), PIC12F1571/2 ONLY 1.6 1.4 Max: 85°C + 3ı Typical: 25°C 1.2 Max. IPD (µA (µA) 1.0 0.8 Typical 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC12(L)F1571/2 FIGURE 27-25: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12LF1571/2 ONLY 28 Max: 85°C + 3ı Typical: 25°C 26 24 Max. IPD (uA) 22 20 18 T i l Typical 16 14 12 10 16 1.6 1 1.8 8 2 2.0 0 2 2.2 2 2 2.4 4 2 2.6 6 2 2.8 8 3 3.0 0 3 3.2 2 3 3.4 4 3 3.6 6 3 3.8 8 VDD (V) FIGURE 27-26: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12F1571/2 ONLY 24 22 Max. 20 IPD (uA (uA) Typical 18 16 14 Max: 85°C + 3ı Typical: 25 C 25°C 12 10 20 2.0 2 5 2.5 3 0 3.0 3 5 3.5 4 0 4.0 4 5 4.5 5 0 5.
PIC12(L)F1571/2 FIGURE 27-27: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC12LF1571/2 ONLY 9 8.5 Max: 85°C + 3ı Typical: 25°C 8 Max. IPD ((uA) 7.5 7 Typical 6.5 6 5.5 5 4.5 24 2.4 2 2.5 5 2 2.6 6 2 2.7 7 2 2.8 8 2 2.9 9 3 3.0 0 3 3.1 1 3 3.2 2 3 3.3 3 3 3.4 4 3 3.5 5 3 3.6 6 3 3.7 7 5 4 5.4 5 6 5.6 VDD (V) IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC12F1571/2 ONLY FIGURE 27-28: 12 11 Max: 85°C + 3ı Typical: 25°C 10 Max. IPD (uA) 9 8 Typical 7 6 5 4 2 8 2.8 3 0 3.0 3 2 3.2 3 4 3.
PIC12(L)F1571/2 FIGURE 27-29: IPD, LOW-POWER BROWN-OUT RESET (LPBOR = 0), PIC12LF1571/2 ONLY 1.8 16 1.6 Max: 85°C + 3ı Typical: 25°C 1.4 Max. IPD (uA (uA) 1.2 1 0.8 0.6 0.4 Typical 0.2 0 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 VDD (V) IPD, LOW-POWER BROWN-OUT RESET (LPBOR = 0), PIC12F1571/2 ONLY FIGURE 27-30: 1.8 Max: 85°C + 3ı Typical: 25°C 1.6 Max. 1.4 IDD (µA (µA) 1.2 1.0 0.8 0.6 Typical 0.4 0.2 0.0 28 2.8 3 3.0 0 3 3.2 2 3 3.4 4 3 3.6 6 3 3.8 8 4 4.
PIC12(L)F1571/2 FIGURE 27-31: IPD, ADC NON-CONVERTING, PIC12LF1571/2 ONLY 500 450 Max: 85°C + 3ı Typical: 25°C 400 Max. 350 IPD (µA) 300 250 200 150 100 Typical 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 27-32: IPD, ADC NON-CONVERTING, PIC12F1571/2 ONLY 1.4 Max: 85°C + 3ı Typical: 25°C 1.2 Max. IDD (µA) 1.0 0.8 0.6 0.4 Typical 0.2 0.0 15 1.5 2 0 2.0 2 5 2.5 3 0 3.0 3 5 3.5 4 0 4.0 4 5 4.5 5 0 5.0 5 5 5.5 6 0 6.
PIC12(L)F1571/2 FIGURE 27-33: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC12F1571/2 ONLY 22 Max: 85°C + 3ı Typical: 25°C 20 Max. 18 Typical IPD (µ (µA) 16 14 12 10 8 6 4 2 0 2.0 2 5 2.5 3 0 3.0 3 5 3.5 4 0 4.0 4 5 4.5 5 0 5.0 5 5 5.5 6 0 6.0 VDD (V) IPD, COMPARATOR, NORMAL POWER MODE (CxSP = 1), PIC12LF1571/2 ONLY FIGURE 27-34: 32 Max: -40°C + 3ı Typical: 25°C 30 28 Max. IPD (µA (µA) 26 24 22 Typical 20 18 16 14 12 16 1.6 1 1.8 8 2 2.0 0 2 2.2 2 2 2.4 4 2 2.6 6 2 2.
PIC12(L)F1571/2 FIGURE 27-35: IPD, COMPARATOR, NORMAL POWER MODE (CxSP = 1), PIC12F1571/2 ONLY 45 Max: -40°C 40°C + 3ı Typical: 25°C 40 Max. 35 IPD (µA (µA) Typical 30 25 20 15 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 FIGURE 27-36: IPD, PWM, HFINTOSC MODE (16 MHz), PIC12LF1571/2 ONLY 1100 Max: 85°C + 3ı Typical: 25°C 1000 900 Max. IPD (µA (µA) 800 700 Typical 600 500 400 300 200 16 1.6 1 8 1.8 2 0 2.0 2 2 2.2 2 4 2.4 2 6 2.6 2 8 2.8 3 0 3.0 3 2 3.2 3 4 3.4 3 6 3.6 3 8 3.8 VDD (V) FIGURE 27-37: IPD, PWM, HFINTOSC MODE (16 MHz), PIC12F1571/2 ONLY 1,200 Max: 85°C + 3ı Typical: 25°C 1,100 Max. 1,000 Typical IPD (µA (µA) 900 800 700 600 500 400 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC12(L)F1571/2 FIGURE 27-38: FVR STABILIZATION PERIOD 60 Max: Typical + 3ı Typical: statistical mean @ 25°C 50 Max. Time (us) 40 Typical 30 20 Note: The FVR Stabilization Period applies when: 1) coming out of RESET or exiting Sleep mode for PIC12/16LFxxxx devices. 2) when exiting sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices In all other cases, the FVR is stable when released from RESET. 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
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PIC12(L)F1571/2 28.
PIC12(L)F1571/2 28.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
PIC12(L)F1571/2 28.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC12(L)F1571/2 28.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
PIC12(L)F1571/2 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (3.90 mm) NNN Legend: XX...
PIC12(L)F1571/2 Package Marking Information (Continued) 8-Lead MSOP (3x3 mm) Example L1571I 310017 8-Lead DFN (3x3x0.9 mm) 8-Lead UDFN (3x3x0.5 mm) XXXX YYWW NNN PIN 1 DS40001723D-page 310 Example MFQ0 1312 017 PIN 1 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 TABLE 29-1: 8-LEAD 3x3x0.9 DFN (MF) TOP MARKING Part Number Marking TABLE 29-2: 8-LEAD 3x3x0.
PIC12(L)F1571/2 29.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No.
PIC12(L)F1571/2 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001723D-page 314 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 & ! " #$% ! " # $ % & "' " " ( $ ) % *++&&& ! !+ $ DS40001723D-page 316 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001723D-page 318 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001723D-page 320 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001723D-page 322 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E NOTE 1 2X 0.10 C 1 2X 2 TOP VIEW 0.10 C 0.05 C C SEATING PLANE A1 A 8X (A3) 0.05 C SIDE VIEW 0.10 C A B D2 1 2 L 0.10 C A B E2 NOTE 1 K N e 8X b 0.
PIC12(L)F1571/2 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Terminals N e Pitch Overall Height A Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width Overall Length D D2 Exposed Pad Length Terminal Width b Terminal Length L K Terminal-to-Exposed-Pad MIN 0.45 0.00 1.40 2.20 0.
PIC12(L)F1571/2 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC12(L)F1571/2 NOTES: DS40001723D-page 326 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (10/2013) Original release of this document. Revision B (2/2014) Updated PIC12(L)F1571/2 Family Types table Program Memory Flash heading (words to K words). Revision C (8/2014) Updated PWM chapter. Changed to Final data sheet. Updated IDD and IPD parameters in the Electrical Specification chapter. Added Characterization Graphs. Added Section Conventions. 1.1: Register and Bit Naming Updated Figures 5-3 and 15-5.
PIC12(L)F1571/2 NOTES: DS40001723D-page 328 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC12(L)F1571/2 NOTES: DS40001723D-page 330 2013-2015 Microchip Technology Inc.
PIC12(L)F1571/2 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
PIC12(L)F1571/2 NOTES: DS40001723D-page 332 2013-2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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