Datasheet

 2013-2015 Microchip Technology Inc. DS80000587C-page 3
PIC12(L)F1571/2
Silicon Errata Issues
1. Module: Enhanced Universal
Synchronous Receiver
Transmitter (EUSART)
1.1 Transmit Mode
Under certain conditions, a byte written to the
TXREG register can be transmitted twice. This
happens when a byte is written to TXREG just as
the TSR register becomes empty. This new byte is
immediately transferred to the TSR register, but
also remains in the TXREG register until the
completion of the current instruction cycle. If the
new byte in the TSR register is transmitted before
this instruction cycle has completed, the duplicate
in the TXREG register will subsequently be
transferred to the TSR register on the following
instruction clock cycle and transmitted.
Work around
When transmitting bytes, it is common practice to
check the TXIF bit before writing to the TXREG
register. To avoid the issue of duplicate bytes
being transmitted, a NOP should be placed before
the write to the TXREG register. This changes the
timing so that the issue does not occur. The TRMT
bit can also be checked in addition to or instead of
the TXIF bit to determine if TXREG can be written
without causing a duplicate-byte transmission. If
the transmit interrupt is enabled then, inside the
ISR, testing the TRMT bit will avoid transmission of
a duplicate byte.
Affected Silicon Revisions
2. Module: 16-Bit Pulse-Width Modulation
(PWM)
2.1 Continuous Run Slave Offset Mode Anomaly
The 16-bit PWM in Continuous Run Slave mode
(PWMxOFTCON<6:5>=11) may get stuck in
anomalous behavior. The behavior is that the
slave PWM output will toggle when the master
PWM matches the master PWM offset value, then
toggle again on the next master offset match
event. The slave PWM output will then remain
steady for the number of master periods equal to
the slave PWM period value, after which the
sequence repeats. The slave PWM may
occasionally start to operate as described by either
writing the slave PWMxOFTCON register or
enabling the slave PWM from an Idle state.
Work around
None.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A0).
A0
X
A0
X