Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MSOP 8 8-Bit 20 MHz I/O number 5

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Table Of Contents

High-Performance RISC CPU:
Flexible Oscillator Structure:
Special Microcontroller Features:
Low-Power Features (PIC12LF1501):
Peripheral Features:
Peripheral Features (Continued):
PIC12(L)F1501/PIC16(L)F150X Family Types
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- TABLE 1-1: Device Peripheral Summary
- FIGURE 1-1: PIC12(L)F1501 Block Diagram
- TABLE 1-2: PIC12(L)F1501 Pinout Description
2.0 Enhanced Mid-Range CPU
- 2.1 Automatic Interrupt Context Saving
- 2.2 16-level Stack with Overflow and Underflow
- 2.3 File Select Registers
- 2.4 Instruction Set
  - FIGURE 2-1: Core Block Diagram
3.0 Memory Organization
- 3.1 Program Memory Organization
- 3.2 Data Memory Organization
- 3.3 PCL and PCLATH
- 3.4 Stack
  - 3.4.1 Accessing the Stack
  - 3.4.2 Overflow/Underflow Reset
- 3.5 Indirect Addressing
4.0 Device Configuration
- 4.1 Configuration Words
  - Register 4-1: CONFIG1: Configuration Word 1
  - Register 4-2: CONFIG2: Configuration Word 2
- 4.2 Code Protection
  - 4.2.1 Program Memory Protection
- 4.3 Write Protection
- 4.4 User ID
- 4.5 Device ID and Revision ID
  - Register 4-3: DEVICEID: Device ID Register
5.0 Oscillator Module
- 5.1 Overview
  - FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram
- 5.2 Clock Source Types
  - 5.2.1 External Clock Sources
    - FIGURE 5-2: External Clock (EC) Mode Operation
  - 5.2.2 Internal Clock Sources
    - FIGURE 5-3: Internal Oscillator Switch Timing
- 5.3 Clock Switching
  - 5.3.1 System Clock Select (SCS) BitS
    - TABLE 5-1: Oscillator Switching Delays
- 5.4 Oscillator Control Registers
6.0 Resets
- FIGURE 6-1: Simplified Block Diagram Of On-Chip Reset Circuit
- 6.1 Power-on Reset (POR)
  - 6.1.1 Power-up Timer (PWRT)
- 6.2 Brown-Out Reset (BOR)
- 6.3 Low-Power Brown-out Reset (LPBOR)
  - 6.3.1 Enabling LPBOR
- 6.4 MCLR
- 6.5 Watchdog Timer (WDT) Reset
- 6.6 RESET Instruction
- 6.7 Stack Overflow/Underflow Reset
- 6.8 Programming Mode Exit
- 6.9 Power-Up Timer
- 6.10 Start-up Sequence
  - FIGURE 6-3: Reset Start-Up Sequence
- 6.11 Determining the Cause of a Reset
  - TABLE 6-3: Reset Status Bits and Their Significance
  - TABLE 6-4: Reset Condition for Special Registers(2)
- 6.12 Power Control (PCON) Register
7.0 Interrupts
- FIGURE 7-1: Interrupt Logic
- 7.1 Operation
- 7.2 Interrupt Latency
  - FIGURE 7-2: Interrupt Latency
  - FIGURE 7-3: INT Pin Interrupt Timing
- 7.3 Interrupts During Sleep
- 7.4 INT Pin
- 7.5 Automatic Context Saving
- 7.6 Interrupt Control Registers
8.0 Power-Down Mode (Sleep)
- 8.1 Wake-up from Sleep
  - 8.1.1 Wake-up Using Interrupts
    - FIGURE 8-1: Wake-Up From Sleep Through Interrupt
- 8.2 Low-Power Sleep Mode
  - 8.2.1 Sleep Current vs. Wake-up Time
  - 8.2.2 Peripheral Usage in Sleep
    - Register 8-1: VREGCON: Voltage Regulator Control Register(1)
    - TABLE 8-1: Summary of Registers Associated with Power-Down Mode
9.0 Watchdog Timer
- FIGURE 9-1: Watchdog Timer Block Diagram
- 9.1 Independent Clock Source
- 9.2 WDT Operating Modes
- 9.3 Time-Out Period
- 9.4 Clearing the WDT
- 9.5 Operation During Sleep
  - TABLE 9-2: WDT Clearing Conditions
- 9.6 Watchdog Control Register
10.0 Flash Program Memory Control
- 10.1 PMADRL and PMADRH Registers
  - 10.1.1 PMCON1 and PMCON2 Registers
- 10.2 Flash Program Memory Overview
- 10.3 Modifying Flash Program Memory
  - FIGURE 10-7: Flash Program Memory Modify Flowchart
- 10.4 User ID, Device ID and Configuration Word Access
  - TABLE 10-2: User ID, Device ID and Configuration Word Access (cfgs = 1)
  - EXAMPLE 10-4: Configuration Word and Device ID Access
- 10.5 Write Verify
  - FIGURE 10-8: Flash Program Memory Verify Flowchart
- 10.6 Flash Program Memory Control Registers
11.0 I/O Ports
- TABLE 11-1: Port Availability Per Device
- FIGURE 11-1: Generic I/O Port Operation
- EXAMPLE 11-1: Initializing PORTA
- 11.1 Alternate Pin Function
  - Register 11-1: APFCON: Alternate Pin Function Control Register
- 11.2 PORTA Registers
  - 11.2.1 ANSELA Register
  - 11.2.2 PORTA Functions and Output Priorities
12.0 Interrupt-On-Change
- 12.1 Enabling the Module
- 12.2 Individual Pin Configuration
- 12.3 Interrupt Flags
- 12.4 Clearing Interrupt Flags
  - EXAMPLE 12-1: Clearing Interrupt Flags (PORTA Example)
- 12.5 Operation in Sleep
  - FIGURE 12-1: Interrupt-On-Change Block Diagram (PORTA Example)
- 12.6 Interrupt-On-Change Registers
13.0 Fixed Voltage Reference (FVR)
- 13.1 Independent Gain Amplifier
- 13.2 FVR Stabilization Period
  - FIGURE 13-1: Voltage Reference Block Diagram
  - TABLE 13-1: Peripherals Requiring the Fixed Voltage Reference (FVR)
- 13.3 FVR Control Registers
  - Register 13-1: FVRCON: Fixed Voltage Reference Control Register
  - TABLE 13-2: Summary of Registers Associated with the Fixed Voltage Reference
14.0 Temperature Indicator Module
- 14.1 Circuit Operation
  - EQUATION 14-1: Vout Ranges
  - FIGURE 14-1: Temperature Circuit Diagram
- 14.2 Minimum Operating Vdd
  - TABLE 14-1: Recommended Vdd vs. Range
- 14.3 Temperature Output
- 14.4 ADC Acquisition Time
  - TABLE 14-2: Summary of Registers Associated with the Temperature Indicator
15.0 Analog-to-Digital Converter (ADC) Module
- FIGURE 15-1: ADC Block Diagram
- 15.1 ADC Configuration
- 15.2 ADC Operation
- 15.3 A/D Acquisition Requirements
16.0 Digital-to-Analog Converter (DAC) Module
- 16.1 Output Voltage Selection
  - EQUATION 16-1: DAC Output Voltage
- 16.2 Ratiometric Output Level
- 16.3 DAC Voltage Reference Output
  - FIGURE 16-1: Digital-to-Analog Converter Block Diagram
  - FIGURE 16-2: Voltage Reference Output Buffer Example
- 16.4 Operation During Sleep
- 16.5 Effects of a Reset
- 16.6 DAC Control Registers
17.0 Comparator Module
- 17.1 Comparator Overview
- 17.2 Comparator Control
- 17.3 Comparator Hysteresis
- 17.4 Timer1 Gate Operation
  - 17.4.1 Comparator Output Synchronization
- 17.5 Comparator Interrupt
- 17.6 Comparator Positive Input Selection
- 17.7 Comparator Negative Input Selection
- 17.8 Comparator Response Time
- 17.9 Analog Input Connection Considerations
18.0 Timer0 Module
- 18.1 Timer0 Operation
- 18.2 Option and Timer0 Control Register
  - Register 18-1: OPTION_REG: OPTION Register
  - TABLE 18-1: Summary of Registers Associated with Timer0
19.0 Timer1 Module with Gate Control
- FIGURE 19-1: Timer1 Block Diagram
- 19.1 Timer1 Operation
  - TABLE 19-1: Timer1 Enable Selections
- 19.2 Clock Source Selection
  - 19.2.1 Internal Clock Source
  - 19.2.2 External Clock Source
    - TABLE 19-2: Clock Source Selections
- 19.3 Timer1 Prescaler
- 19.4 Timer1 Operation in Asynchronous Counter Mode
  - 19.4.1 Reading and Writing Timer1 in Asynchronous Counter Mode
- 19.5 Timer1 Gate
- 19.6 Timer1 Interrupt
- 19.7 Timer1 Operation During Sleep
  - 19.7.1 Alternate Pin Locations
- 19.8 Timer1 Control Registers
20.0 Timer2 Module
- FIGURE 20-1: Timer2 Block Diagram
- 20.1 Timer2 Operation
- 20.2 Timer2 Interrupt
- 20.3 Timer2 Output
- 20.4 Timer2 Operation During Sleep
  - Register 20-1: T2CON: Timer2 Control Register
  - TABLE 20-1: Summary of Registers Associated With Timer2
21.0 Pulse-Width Modulation (PWM) Module
- FIGURE 21-1: PWM Output
- FIGURE 21-2: Simplified PWM Block Diagram
- 21.1 PWMx Pin Configuration
- 21.2 PWM Register Definitions
22.0 Configurable Logic Cell (CLC)
- FIGURE 22-1: CLCx Simplified Block Diagram
- 22.1 CLCx Setup
- 22.2 CLCx Interrupts
- 22.3 Output Mirror Copies
- 22.4 Effects of a Reset
- 22.5 Operation During Sleep
- 22.6 Alternate Pin Locations
  - FIGURE 22-2: Input Data Selection and Gating
  - FIGURE 22-3: Programmable Logic Functions
- 22.7 CLCx Control Registers
23.0 Numerically Controlled Oscillator (NCO) Module
- FIGURE 23-1: Numerically Controlled Oscillator (NCOx) Module Simplified Block Diagram
- 23.1 NCOx OPERATION
- 23.2 FIXED DUTY CYCLE (FDC) MODE
- 23.3 PULSE FREQUENCY (PF) MODE
  - 23.3.1 Output Pulse Width Control
- 23.4 OUTPUT POLARITY CONTROL
  - FIGURE 23-2: FDC Output Mode Operation Diagram
- 23.5 Interrupts
- 23.6 Effects of a Reset
- 23.7 Operation In Sleep
- 23.8 Alternate Pin Locations
- 23.9 NCOx Control Registers
24.0 Complementary Waveform Generator (CWG) Module
- FIGURE 24-1: Simplified CWG Block Diagram
- FIGURE 24-2: Typical CWG Operation with PWM1 (no Auto-shutdown)
- 24.1 Fundamental Operation
- 24.2 Clock Source
- 24.3 Selectable Input Sources
- 24.4 Output Control
  - 24.4.1 Output Enables
  - 24.4.2 Polarity Control
- 24.5 Dead-Band Control
- 24.6 Rising Edge Dead Band
- 24.7 Falling Edge Dead Band
- 24.8 Dead-Band Uncertainty
- 24.9 Auto-shutdown Control
  - 24.9.1 SHUTDOWN
- 24.10 Operation During Sleep
- 24.11 Alternate Pin Locations
- 24.12 Configuring the CWG
  - 24.12.1 PIN OVERRIDE LEVELS
  - 24.12.2 AUTO-SHUTDOWN RESTART
    - FIGURE 24-5: SHUTDOWN Functionality, Auto-restart Disabled (GxARSEN = 0,GxASDLA = 01, GxASDLB = 01)
    - FIGURE 24-6: SHUTDOWN Functionality, Auto-restart Enabled (GxARSEN = 1,GxASDLA = 01, GxASDLB = 01)
- 24.13 CWG Control Registers
25.0 In-Circuit Serial Programming™ (ICSP™)
- 25.1 High-Voltage Programming Entry Mode
- 25.2 Low-Voltage Programming Entry Mode
- 25.3 Common Programming Interfaces
26.0 Instruction Set Summary
- 26.1 Read-Modify-Write Operations
- 26.2 Instruction Descriptions
27.0 Electrical Specifications
- Absolute Maximum Ratings(†)
  - FIGURE 27-1: PIC12F1501 Voltage Frequency Graph, -40°C £ Ta £ +125°C
  - FIGURE 27-2: PIC12LF1501 Voltage Frequency Graph, -40°C £ Ta £ +125°C
- 27.1 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended)
  - FIGURE 27-3: POR and POR Rearm with Slow Rising Vdd
- 27.2 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended)
- 27.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down)
- 27.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down) (Continued)
- 27.4 DC Characteristics: PIC12(L)F1501-I/E
- 27.5 Memory Programming Requirements
- 27.6 Thermal Considerations
- 27.7 Timing Parameter Symbology
  - FIGURE 27-4: Load Conditions
- 27.8 AC Characteristics: PIC12(L)F1501-I/E
28.0 DC and AC Characteristics Graphs and Charts
- 29.0 Development Support
30.0 Packaging Information
- 30.1 Package Marking Information
- Package Marking Information (Continued)
  - TABLE 30-1: 8-Lead 2X3 Dfn (mc) tOP mARKINg
  - TABLE 30-2: 8-Lead 3X3 Qfn (mF) tOP mARKINg
- 30.2 Package Details
Appendix A: Data Sheet Revision History
- Revision A
INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
Product Identification System
Worldwide Sales and Service

 2011 Microchip Technology Inc. Preliminary DS41615A-page 271

PIC12(L)F1501

MCLR .................................................................................. 56

Internal........................................................................ 56

Memory Organization.......................................................... 15

Data ............................................................................ 17

Program ...................................................................... 15

Microchip Internet Web Site.............................................. 275

MOVIW ............................................................................. 220

MOVLB ............................................................................. 220

MOVWI ............................................................................. 221

MPLAB ASM30 Assembler, Linker, Librarian ................... 250

MPLAB Integrated Development Environment Software .. 249

MPLAB PM3 Device Programmer .................................... 252

MPLAB REAL ICE In-Circuit Emulator System................. 251

MPLINK Object Linker/MPLIB Object Librarian ................ 250

NCO

Associated registers.................................................. 192

NCOxACCH Register........................................................ 190

NCOxACCL Register ........................................................ 190

NCOxACCU Register........................................................ 190

NCOxCLK Register........................................................... 189

NCOxCON Register.......................................................... 189

NCOxINCH Register ......................................................... 191

NCOxINCL Register.......................................................... 191

Numerically Controlled Oscillator (NCO)........................... 183

OPCODE Field Descriptions............................................. 211

OPTION ............................................................................221

OPTION Register.............................................................. 143

OSCCON Register.............................................................. 51

Oscillator

Associated Registers .................................................. 52

Associated registers.................................................. 207

Oscillator Module ................................................................ 45

ECH ............................................................................ 45

ECL............................................................................. 45

ECM............................................................................ 45

INTOSC ...................................................................... 45

Oscillator Parameters ....................................................... 238

Oscillator Specifications.................................................... 238

Oscillator Start-up Timer (OST)

Specifications............................................................ 241

OSCSTAT Register............................................................. 52

Packaging ......................................................................... 253

Marking ............................................................. 253, 254

PDIP Details.............................................................. 255

PCL and PCLATH............................................................... 14

PCL Register....................................................................... 24

PCLATH Register ............................................................... 24

PCON Register ............................................................. 25, 59

PIE1 Register................................................................ 25, 67

PIE2 Register................................................................ 25, 68

PIE3 Register................................................................ 25, 69

PIR1 Register................................................................ 25, 70

PIR2 Register................................................................ 25, 71

PIR3 Register................................................................ 25, 72

PMADR Registers............................................................... 83

PMADRH Registers ............................................................ 83

PMADRL Register............................................................... 96

PMADRL Registers............................................................. 83

PMCON1 Register........................................................ 83, 97

PMCON2 Register........................................................ 83, 98

PMDATH Register .............................................................. 96

PMDATL Register............................................................... 96

PMDRH Register ................................................................ 96

PORTA ............................................................................. 101

ANSELA Register..................................................... 101

Associated Registers................................................ 104

LATA Register ............................................................ 26

PORTA Register......................................................... 25

Specifications ........................................................... 239

PORTA Register............................................................... 102

Power-Down Mode (Sleep)................................................. 75

Associated Registers.................................................. 78

Power-on Reset.................................................................. 54

Power-up Time-out Sequence ............................................ 56

Power-up Timer (PWRT) .................................................... 54

Specifications ........................................................... 241

PR2 Register ...................................................................... 25

Program Memory................................................................ 15

Map and Stack (PIC12(L)F1501................................. 16

Programming, Device Instructions.................................... 211

Pulse Width Modulation (PWM)........................................ 161

Associated registers w/ PWM................................... 166

PWM Mode

Duty Cycle ........................................................ 162

Effects of Reset ................................................ 163

Example PWM Frequencies and

Resolutions, 20 MHZ................................ 163

Example PWM Frequencies and

Resolutions, 8 MHz .................................. 163

Operation in Sleep Mode.................................. 163

Setup for Operation using PWMx pins ............. 164

System Clock Frequency Changes .................. 163

PWM Period ............................................................. 162

Setup for PWM Operation using PWMx Pins ........... 164

PWMxCON Register......................................................... 165

PWMxDCH Register ......................................................... 166

PWMxDCL Register.......................................................... 166

Reader Response............................................................. 276

Read-Modify-Write Operations ......................................... 211

Registers

ADCON0 (ADC Control 0) ........................................ 119

ADCON1 (ADC Control 1) ........................................ 120

ADCON2 (ADC Control 2) ........................................ 121

ADRESH (ADC Result High) with ADFM = 0) .......... 122

ADRESH (ADC Result High) with ADFM = 1) .......... 123

ADRESL (ADC Result Low) with ADFM = 0)............ 122

ADRESL (ADC Result Low) with ADFM = 1)............ 123

ANSELA (PORTA Analog Select) ............................ 103

APFCON (Alternate Pin Function Control) ............... 100

BORCON Brown-out Reset Control) .......................... 55

CLCDATA (Data Output) .......................................... 181

CLCxCON (CLCx Control)........................................ 173

CLCxGLS0 (Gate 1 Logic Select)............................. 177

CLCxGLS1 (Gate 2 Logic Select)............................. 178

CLCxGLS2 (Gate 3 Logic Select)............................. 179

CLCxGLS3 (Gate 4 Logic Select)............................. 180

CLCxPOL (Signal Polarity Control) .......................... 174

CLCxSEL0 (Multiplexer Data 1 and 2 Select) .......... 175

CMOUT (Comparator Output) .................................. 138

CMxCON0 (Cx Control)............................................ 137

CMxCON1 (Cx Control 1)......................................... 138

Configuration Word 1.................................................. 40