Datasheet
Table Of Contents
- High-Performance RISC CPU:
- Flexible Oscillator Structure:
- Special Microcontroller Features:
- Low-Power Features (PIC12LF1501):
- Peripheral Features:
- Peripheral Features (Continued):
- PIC12(L)F1501/PIC16(L)F150X Family Types
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 Device Overview
- 2.0 Enhanced Mid-Range CPU
- 3.0 Memory Organization
- 4.0 Device Configuration
- 5.0 Oscillator Module
- 6.0 Resets
- FIGURE 6-1: Simplified Block Diagram Of On-Chip Reset Circuit
- 6.1 Power-on Reset (POR)
- 6.2 Brown-Out Reset (BOR)
- 6.3 Low-Power Brown-out Reset (LPBOR)
- 6.4 MCLR
- 6.5 Watchdog Timer (WDT) Reset
- 6.6 RESET Instruction
- 6.7 Stack Overflow/Underflow Reset
- 6.8 Programming Mode Exit
- 6.9 Power-Up Timer
- 6.10 Start-up Sequence
- 6.11 Determining the Cause of a Reset
- 6.12 Power Control (PCON) Register
- 7.0 Interrupts
- 8.0 Power-Down Mode (Sleep)
- 9.0 Watchdog Timer
- 10.0 Flash Program Memory Control
- 10.1 PMADRL and PMADRH Registers
- 10.2 Flash Program Memory Overview
- 10.3 Modifying Flash Program Memory
- 10.4 User ID, Device ID and Configuration Word Access
- 10.5 Write Verify
- 10.6 Flash Program Memory Control Registers
- Register 10-1: PMDATL: Program Memory Data Low Byte Register
- Register 10-2: PMDATH: Program Memory Data hIGH bYTE Register
- Register 10-3: PMADRL: Program Memory Address Low Byte Register
- Register 10-4: PMADRH: Program Memory Address hIGH bYTE Register
- Register 10-5: PMCON1: Program Memory Control 1 Register
- Register 10-6: PMCON2: Program Memory Control 2 Register
- TABLE 10-3: Summary of Registers Associated with Flash Program Memory
- TABLE 10-4: Summary of Configuration Word with Flash Program Memory
- 11.0 I/O Ports
- TABLE 11-1: Port Availability Per Device
- FIGURE 11-1: Generic I/O Port Operation
- EXAMPLE 11-1: Initializing PORTA
- 11.1 Alternate Pin Function
- 11.2 PORTA Registers
- 11.2.1 ANSELA Register
- 11.2.2 PORTA Functions and Output Priorities
- TABLE 11-2: PORTA Output Priority
- Register 11-2: PORTA: PORTA Register
- Register 11-3: TRISA: PORTA Tri-State Register
- Register 11-4: LATA: PORTA Data Latch Register
- Register 11-5: ANSELA: PORTA Analog Select Register
- Register 11-6: WPUA: Weak Pull-Up PORTA Register
- TABLE 11-3: Summary of Registers Associated with PORTA
- TABLE 11-4: Summary of Configuration Word with PORTA
- 12.0 Interrupt-On-Change
- 13.0 Fixed Voltage Reference (FVR)
- 14.0 Temperature Indicator Module
- 15.0 Analog-to-Digital Converter (ADC) Module
- FIGURE 15-1: ADC Block Diagram
- 15.1 ADC Configuration
- 15.2 ADC Operation
- 15.2.1 Starting a Conversion
- 15.2.2 Completion of a Conversion
- 15.2.3 Terminating a conversion
- 15.2.4 ADC Operation During Sleep
- 15.2.5 Auto-Conversion Trigger
- 15.2.6 A/D Conversion Procedure
- 15.2.7 ADC Register Definitions
- Register 15-1: ADCON0: A/D Control Register 0
- Register 15-2: ADCON1: A/D Control Register 1
- Register 15-3: ADCON2: A/D Control Register 2
- Register 15-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0
- Register 15-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0
- Register 15-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1
- Register 15-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1
- 15.3 A/D Acquisition Requirements
- 16.0 Digital-to-Analog Converter (DAC) Module
- 17.0 Comparator Module
- 18.0 Timer0 Module
- 19.0 Timer1 Module with Gate Control
- 20.0 Timer2 Module
- 21.0 Pulse-Width Modulation (PWM) Module
- FIGURE 21-1: PWM Output
- FIGURE 21-2: Simplified PWM Block Diagram
- 21.1 PWMx Pin Configuration
- 21.2 PWM Register Definitions
- 22.0 Configurable Logic Cell (CLC)
- FIGURE 22-1: CLCx Simplified Block Diagram
- 22.1 CLCx Setup
- 22.2 CLCx Interrupts
- 22.3 Output Mirror Copies
- 22.4 Effects of a Reset
- 22.5 Operation During Sleep
- 22.6 Alternate Pin Locations
- 22.7 CLCx Control Registers
- Register 22-1: CLCxCON: Configurable Logic CELL Control Register
- Register 22-2: CLCxPOL: Signal Polarity Control Register
- Register 22-3: CLCxSEL0: MULTIPLEXER DATA 1 and 2 SELECT Register
- Register 22-4: CLCxSEL1: MULTIPLEXER DATA 3 and 4 SELECT Register
- Register 22-5: CLCxGLS0: Gate 1 Logic Select Register
- Register 22-6: CLCxGLS1: Gate 2 Logic Select Register
- Register 22-7: CLCxGLS2: Gate 3 Logic Select Register
- Register 22-8: CLCxGLS3: Gate 4 Logic Select Register
- Register 22-9: CLCDATA: CLC Data Output
- TABLE 22-3: Summary Of Registers Associated With CLCx
- 23.0 Numerically Controlled Oscillator (NCO) Module
- FIGURE 23-1: Numerically Controlled Oscillator (NCOx) Module Simplified Block Diagram
- 23.1 NCOx OPERATION
- 23.2 FIXED DUTY CYCLE (FDC) MODE
- 23.3 PULSE FREQUENCY (PF) MODE
- 23.4 OUTPUT POLARITY CONTROL
- 23.5 Interrupts
- 23.6 Effects of a Reset
- 23.7 Operation In Sleep
- 23.8 Alternate Pin Locations
- 23.9 NCOx Control Registers
- Register 23-1: NCOxCON: NCOx Control Register
- Register 23-2: NCOxCLK: NCOx Input Clock Control Register
- Register 23-3: NCOxACCL: NCOx Accumulator Register – Low Byte
- Register 23-4: NCOxACCH: NCOx Accumulator Register – High Byte
- Register 23-5: NCOxACCU: NCOx Accumulator Register – Upper Byte
- Register 23-6: NCOxINCL: NCOx Increment Register – Low Byte
- Register 23-7: NCOxINCH: NCOx Increment Register – High Byte
- TABLE 23-1: Summary of Registers Associated with NCOx
- 24.0 Complementary Waveform Generator (CWG) Module
- FIGURE 24-1: Simplified CWG Block Diagram
- FIGURE 24-2: Typical CWG Operation with PWM1 (no Auto-shutdown)
- 24.1 Fundamental Operation
- 24.2 Clock Source
- 24.3 Selectable Input Sources
- 24.4 Output Control
- 24.5 Dead-Band Control
- 24.6 Rising Edge Dead Band
- 24.7 Falling Edge Dead Band
- 24.8 Dead-Band Uncertainty
- 24.9 Auto-shutdown Control
- 24.10 Operation During Sleep
- 24.11 Alternate Pin Locations
- 24.12 Configuring the CWG
- 24.13 CWG Control Registers
- Register 24-1: CWGxCON0: CWG Control Register 0
- Register 24-2: CWGxCON1: CWG Control Register 1
- Register 24-3: CWGXCON2: CWG Control Register 2
- Register 24-4: CWGxDBR: Complementary Waveform Generator (CWGx) Rising Dead-band Count Register
- Register 24-5: CWGxdbf: Complementary Waveform Generator (CWGx) Falling Dead-Band Count Register
- 24.13.1 Alternate Pin Locations
- 25.0 In-Circuit Serial Programming™ (ICSP™)
- 26.0 Instruction Set Summary
- 27.0 Electrical Specifications
- Absolute Maximum Ratings(†)
- 27.1 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended)
- 27.2 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended)
- 27.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down)
- 27.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down) (Continued)
- 27.4 DC Characteristics: PIC12(L)F1501-I/E
- 27.5 Memory Programming Requirements
- 27.6 Thermal Considerations
- 27.7 Timing Parameter Symbology
- 27.8 AC Characteristics: PIC12(L)F1501-I/E
- FIGURE 27-5: Clock Timing
- TABLE 27-1: Clock Oscillator Timing Requirements
- TABLE 27-2: Oscillator Parameters
- FIGURE 27-6: CLKOUT and I/O Timing
- TABLE 27-3: CLKOUT and I/O Timing Parameters
- FIGURE 27-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
- FIGURE 27-8: Brown-Out Reset Timing and Characteristics
- TABLE 27-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters
- FIGURE 27-9: Timer0 and Timer1 External Clock Timings
- TABLE 27-5: Timer0 and Timer1 External Clock Requirements
- TABLE 27-6: PIC12(L)F1501 A/D Converter (ADC) Characteristics:
- TABLE 27-7: PIC12(L)F1501 A/D Conversion Requirements
- FIGURE 27-10: PIC12(L)F1501 A/D Conversion Timing (Normal Mode)
- FIGURE 27-11: PIC12(L)F1501 A/D Conversion Timing (Sleep Mode)
- TABLE 27-8: Comparator Specifications
- TABLE 27-9: Digital-to-Analog Converter (DAC) Specifications
- 28.0 DC and AC Characteristics Graphs and Charts
- 30.0 Packaging Information
- Appendix A: Data Sheet Revision History
- INDEX
- Product Identification System
- Worldwide Sales and Service

2011 Microchip Technology Inc. Preliminary DS41615A-page 17
PIC12(L)F1501
3.1.1.2 Indirect Read with FSR
The program memory can be accessed as data by set-
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates access-
ing the program memory via an FSR.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2: ACCESSING PROGRAM
MEMORY VIA FSR
3.2 Data Memory Organization
The data memory is partitioned into 32 memory banks
with 128 bytes in each bank. Each bank consists of
(Figure 3-2):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect
Addressing” for more information.
Data memory uses a 12-bit address. The upper 7 bits
of the address define the Bank address and the lower
5 bits select the registers/RAM in that bank.
3.2.1 CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Ta bl e 3- 2. For detailed
information, see Table 3- 4.
TABLE 3-2: CORE REGISTERS
constants
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
Addresses BANKx
x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON