Datasheet

PIC12(L)F1501
DS41615A-page 168 Preliminary  2011 Microchip Technology Inc.
22.1 CLCx Setup
Programming the CLCx module is performed by config-
uring the 4 stages in the logic signal flow. The 4 stages
are:
•Data selection
• Data gating
• Logic function selection
• Output polarity
Each stage is setup at run time by writing to the corre-
sponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
22.1.1 DATA SELECTION
There are 16 signals available as inputs to the configu-
rable logic. Four 8-input multiplexers are used to select
the inputs to pass on to the next stage. The 16 inputs to
the multiplexers are arranged in groups of four. Each
group is available to two of the four multiplexers, in
each case, paired with a different group. This arrange-
ment makes possible selection of up to two from a
group without precluding a selection from another
group.
Data inputs are selected with the CLCxSEL0 and
CLCxSEL1 registers (Register 22-3 and Register 22-4,
respectively).
Data inputs are selected with CLCxSEL0 and
CLCxSEL1 registers (Register 22-3 and Register 22-4,
respectively).
Data selection is through four multiplexers as indicated
on the left side of Figure 22-2. Data inputs in the figure
are identified by a generic numbered input name.
Table 22-1 correlates the generic input name to the
actual signal for each CLC module. The columns labeled
lcxd1 through lcxd4 indicate the MUX output for the
selected data input. D1S through D4S are abbreviations
for the MUX select input codes: LCxD1S<2:0> through
LCxD4S<2:0>, respectively. Selecting a data input in a
column excludes all other inputs in that column.
Note: Data selections are undefined at power-up.
TABLE 22-1: CLCx DATA INPUT SELECTION
Data Input
lcxd1
D1S
lcxd2
D2S
lcxd3
D3S
lcxd4
D4S
CLC 1 CLC 2
CLCxIN[0] 000 — — 100 CLC1IN0 CLC2IN0
CLCxIN[1] 001
— — 101 CLC1IN1 CLC2IN1
CLCxIN[2] 010
— — 110 sync_C1OUT sync_C1OUT
CLCxIN[3] 011
— — 111 Reserved Reserved
CLCxIN[4] 100 000
— —FOSC FOSC
CLCxIN[5] 101 001 — — TMR0IF TMR0IF
CLCxIN[6] 110 010
— — TMR1IF TMR1IF
CLCxIN[7] 111 011
— — TMR2 = PR2 TMR2 = PR2
CLCxIN[8]
— 100 000 — lc1_out lc1_out
CLCxIN[9]
— 101 001 — lc2_out lc2_out
CLCxIN[10]
— 110 010 — Reserved Reserved
CLCxIN[11]
— 111 011 — Reserved Reserved
CLCxIN[12]
— — 100 000 NCO1OUT LFINTOSC
CLCxIN[13]
— — 101 001 HFINTOSC ADFRC
CLCxIN[14]
— — 110 010 PWM3OUT PWM1OUT
CLCxIN[15]
— — 111 011 PWM4OUT PWM2OUT