PIC12(L)F1501 Data Sheet 8-Pin Flash, 8-Bit Microcontrollers *8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC12(L)F1501 8-Pin Flash, 8-Bit Microcontrollers High-Performance RISC CPU: Low-Power Features (PIC12LF1501): • • • • • • Standby Current: - 20 nA @ 1.8V, typical • Watchdog Timer Current: - 200 nA @ 1.8V, typical • Operating Current: - 30 A/MHz @ 1.
PIC12(L)F1501 Peripheral Features (Continued): • Numerically Controlled Oscillator (NCO): - 20-bit accumulator - 16-bit increment - True linear frequency control - High-speed clock input - Selectable Output modes: - Fixed Duty Cycle (FDC) mode - Pulse Frequency (PF) mode • Complementary Waveform Generator (CWG): - 8 selectable signal sources - Selectable falling and rising edge dead-band control - Polarity control - 4 auto-shutdown sources - Multiple input sources: PWM, CLC, NCO DS41615A-page 4 Preliminar
PIC12(L)F1501 FIGURE 1: 8-PIN PDIP, SOIC, MSOP, DFN DIAGRAM FOR PIC12(L)F1501 VDD 1 RA5 2 RA4 3 MCLR/VPP/RA3 4 PIC12(L)F1501 PDIP, SOIC, MSOP, DFN 8 VSS 7 RA0/ICSPDAT 6 RA1/ICSPCLK 5 RA2 Note: See Table 1 for location of all peripheral functions.
PIC12(L)F1501 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13 3.0 Memory Organization ................................................................................
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PIC12(L)F1501 NOTES: DS41615A-page 8 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 1.0 DEVICE OVERVIEW The PIC12(L)F1501 are described within this data sheet. They are available in 14-pin packages. Figure 1-1 shows a block diagram of the PIC12(L)F1501 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device.
PIC12(L)F1501 FIGURE 1-1: PIC12(L)F1501 BLOCK DIAGRAM Program Flash Memory RAM CLKOUT Timing Generation CLKIN INTRC Oscillator PORTA CPU (Figure 2-1) MCLR C1 Temp. Indicator Note DS41615A-page 10 1: 2: CLC1 ADC 10-Bit CLC2 FVR Timer0 Timer1 PWM1 Timer2 PWM2 CWG1 PWM3 NCO1 PWM4 DAC See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 TABLE 1-2: PIC12(L)F1501 PINOUT DESCRIPTION Name RA0/AN0/C1IN+/DACOUT1/ CWG1B(1)/CLC2IN1/PWM2/ ICSPDAT RA1/AN1/VREF+/C1IN0-/ NCO1(1)/CLC2IN0/ICSPCLK RA2/AN2/C1OUT/DACOUT2/ T0CKI/INT/PWM1/CLC1(1)/ CWG1A(1)/CWG1FLT RA3/CLC1IN0/VPP/T1G(2)/MCLR (2) RA4/AN3/C1IN1-/CWG1B / CLC1(2)/PWM3/CLKOUT/T1G(1) Function Input Type RA0 TTL AN0 AN Output Type Description CMOS General purpose I/O. — A/D Channel input. C1IN+ AN — Comparator positive input.
PIC12(L)F1501 TABLE 1-2: PIC12(L)F1501 PINOUT DESCRIPTION (CONTINUED) Function Input Type RA5 TTL CLKIN CMOS — External clock input (EC mode). T1CKI ST — Timer1 clock input. CWG1A — NCO1 ST — Numerically Controlled Oscillator output. NCO1CLK ST — Numerically Controlled Oscillator Clock source input. CLC1IN1 ST — Configurable Logic Cell source input. CLC2 — CMOS Configurable Logic Cell source output. PWM4 — CMOS Pulse Width Module source output.
PIC12(L)F1501 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.
PIC12(L)F1501 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 CLKIN CLKOUT Instruction Decodeand & Decode Control Timing Generation Internal Oscillator Block DS41615A-p
PIC12(L)F1501 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM TABLE 3-1: Device • PCL and PCLATH • Stack • Indirect Addressing 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space.
PIC12(L)F1501 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC12(L)F1501 PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE On-chip Program Memory 15 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction Stack Level 0 Stack Level 1 The RETLW instruction can be used to provide access to tables of constants.
PIC12(L)F1501 3.1.1.2 Indirect Read with FSR 3.2.1 The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.
PIC12(L)F1501 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC12(L)F1501 3.2.2 SPECIAL FUNCTION REGISTER FIGURE 3-2: The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.
DS41615A-page 20 Preliminary — — — PORTA — — — — PIR1 PIR2 PIR3 — TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON Core Registers (Table 3-2) 0FFh 0EFh 0F0h Common RAM (Accesses 70h – 7Fh) Unimplemented Read as ‘0’ ADCON0 ADCON1 ADCON2 TRISA — — — — PIE1 PIE2 PIE3 — OPTION_REG PCON WDTCON — OSCCON OSCSTAT ADRESL ADRESH Core Registers (Table 3-2) BANK 1 17Fh 16Fh 170h 11Dh 11Eh 11Fh 120h 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 100h Common RAM (A
2011 Microchip Technology Inc.
DS41615A-page 22 Preliminary Legend: CFFh C6Fh C70h C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h C00h CFFh CEFh CF0h C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Common RAM (Accesses 70h – 7Fh) Unimplemented Read as ‘0’ — — — — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) BANK 25 D7Fh D6Fh D70h D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h
PIC12(L)F1501 TABLE 3-3: PIC12(L)F1501 MEMORY MAP (CONTINUED) Bank 30 F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F6Fh Legend: Bank 31 — — — CLCDATA CLC1CON CLC1POL CLC1SEL0 CLC1SEL1 CLC1GLS0 CLC1GLS1 CLC1GLS2 CLC1GLS3 CLC2CON CLC2POL CLC2SEL0 CLC2SEL1 CLC2GLS0 CLC2GLS1 CLC2GLS2 CLC2GLS3 F8Ch Unimplemented Read as ‘0’ FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H
PIC12(L)F1501 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-4 can be addressed from any Bank.
PIC12(L)F1501 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY Name Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx Bank 0 00Ch PORTA 00Dh — Unimplemented — — 00Eh — Unimplemented — — 00Fh — Unimplemented — — 010h — Unimplemented — — 011h PIR1 TMR1GIF ADIF — — — — TMR2IF TMR1IF 00-- --00 00-- --00 012h PIR2 — — C1IF — — NCO1IF — — --0- -0-- --0- -0-
PIC12(L)F1501 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — LATA5 LATA4 — LATA2 LATA1 LATA0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA 10Dh — Unimplemented — — 10Eh — Unimplemented — — 10Fh — Unimplemented — — 110h — Unimplemented — — 111h CM1CON0 112h CM1CON1 113h — Unimplemented — — 114h — Unimplemented — — 115h CMOUT 116h BORCON SBOREN BORFS 117h FV
PIC12(L)F1501 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 Value on POR, BOR Value on all other Resets Bank 4 20Ch 20Dh to 21Fh WPUA --11 1111 --11 1111 — Unimplemented — — — Unimplemented — — — Unimplemented — — — Unimplemented — — Bank 5 28Ch to 29Fh Bank 6 30Ch to 31Fh Bank 7 38Ch to 390h 391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP
PIC12(L)F1501 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — Unimplemented — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 10 50Ch to 51Fh — Bank 11 58Ch to 59Fh — Bank 12 60Ch to 610h — 611h PWM1DCL 612h PWM1DCH 613h PWM1CON0 614h PWM2DCL 615h PWM2DCH 616h PWM2CON0 617h PWM3DCL 618h PWM3DCH 619h PWM3CON0 61Ah PWM4DCL 61Bh PWM4DCH 61Ch PWM4CON0 6
PIC12(L)F1501 TABLE 3-5: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Banks 14-29 x0Ch/ x8Ch — x1Fh/ x9Fh — Bank 30 F0Ch to F0Eh — F0Fh CLCDATA — — — — — F10h CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN F11h CLC1POL LC1POL — — — — MLC1OUT MLC2OUT LC1MODE<2:0> LC1G4POL LC1G3POL LC1G2POL ---- --00 ---- --00 0000 0000 0000 00
PIC12(L)F1501 TABLE 3-5: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 31 F8Ch — FE3h — FE4h STATUS_ Unimplemented — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Shadow xxxx xxxx uuuu uuuu SHAD FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ — Program Counter Latch High Register Shad
PIC12(L)F1501 3.3 PCL and PCLATH 3.3.2 The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC.
PIC12(L)F1501 3.4 Stack 3.4.1 The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow.
PIC12(L)F1501 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
PIC12(L)F1501 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.
PIC12(L)F1501 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. 2011 Microchip Technology Inc.
PIC12(L)F1501 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
PIC12(L)F1501 3.5.2 3.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC12(L)F1501 NOTES: DS41615A-page 38 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. 2011 Microchip Technology Inc.
PIC12(L)F1501 REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 U-1 U-1 R/P-1 — — CLKOUTEN R/P-1 R/P-1 U-1 BOREN<1:0> — bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 8 R/P-1 R/P-1 U-1 WDTE<1:0> R/P-1 R/P-1 FOSC<1:0> — bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13-12 Unimplemented: Read as ‘1’ bit 11 CLKOUTEN: Clock Out Enable bit 1 = CLKOUT functi
PIC12(L)F1501 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1 LVP — LPBOR BORV STVREN — bit 13 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR mus
PIC12(L)F1501 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s.
PIC12(L)F1501 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.
PIC12(L)F1501 NOTES: DS41615A-page 44 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 5.0 OSCILLATOR MODULE The oscillator module can be configured in one of the following clock modes. 5.1 Overview 1. The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. 2. 3. 4. ECL – External Clock Low-Power mode (0 MHz to 0.5 MHz) ECM – External Clock Medium-Power mode (0.
PIC12(L)F1501 5.2 Clock Source Types 5.2.1.1 Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode). Internal clock sources are contained within the oscillator module.
PIC12(L)F1501 5.2.2 INTERNAL CLOCK SOURCES 5.2.2.2 The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<1:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.
PIC12(L)F1501 5.2.2.3 Internal Oscillator Frequency Selection 5.2.2.4 The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The outputs of the 16 MHz HFINTOSC postscaler and the LFINTOSC connect to a multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators.
PIC12(L)F1501 FIGURE 5-3: HFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC LFINTOSC (WDT enabled) HFINTOSC LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <3:0> =0 0 System Clock 2011 Microchip Technology Inc.
PIC12(L)F1501 5.3 Clock Switching 5.3.1 The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register.
PIC12(L)F1501 5.
PIC12(L)F1501 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER U-0 U-0 U-0 R-0/q U-0 U-0 R-0/q R-0/q — — — HFIOFR — — LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7-5 Unimplemented: Read as ‘0’ bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = 16 MHz Inter
PIC12(L)F1501 6.0 RESETS There are multiple ways to reset this device: • • • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-chip Reset Circuit is shown in Figure 6-1.
PIC12(L)F1501 6.1 Power-on Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC12(L)F1501 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal < TPWRT Reset TPWRT(1) VDD VBOR Internal Reset Note 1: TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
PIC12(L)F1501 6.3 Low-Power Brown-out Reset (LPBOR) 6.5 The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 6-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 6-2. 6.3.
PIC12(L)F1501 FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2011 Microchip Technology Inc.
PIC12(L)F1501 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers.
PIC12(L)F1501 6.12 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 6-2.
PIC12(L)F1501 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 55 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 59 STATUS — — — TO PD Z DC C 18 WDTCON — — SWDTEN 81 WDTPS<4:0> Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
PIC12(L)F1501 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details.
PIC12(L)F1501 7.1 Operation 7.2 Interrupts are disabled upon any device Reset.
PIC12(L)F1501 FIGURE 7-2: INTERRUPT LATENCY Fosc Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP
PIC12(L)F1501 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC CLKOUT (3) INT pin (1) (1) INTF Interrupt Latency (2) (4) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Forced NOP 0004h 0005h Inst (0004h) Inst (0005h) Forced NOP Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY.
PIC12(L)F1501 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC12(L)F1501 7.6 Interrupt Control Registers 7.6.1 Note: INTCON REGISTER The INTCON register is a readable and writable register, that contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 7-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register.
PIC12(L)F1501 7.6.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 7-2. REGISTER 7-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC12(L)F1501 7.6.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 7-3. REGISTER 7-3: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC12(L)F1501 7.6.4 PIE3 REGISTER The PIE3 register contains the interrupt enable bits, as shown in Register 7-4. REGISTER 7-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC12(L)F1501 7.6.5 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 7-5. REGISTER 7-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC12(L)F1501 7.6.6 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 7-6. REGISTER 7-6: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC12(L)F1501 7.6.7 PIR3 REGISTER The PIR3 register contains the interrupt flag bits, as shown in Register 7-7. REGISTER 7-7: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC12(L)F1501 TABLE 7-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66 OPTION_REG WPUEN PIE1 TMR1GIE INTEDG TMR0CS TMR0SE PSA PS<2:0> ADIE — — — — TMR2IE 143 TMR1IE 67 PIE2 — — C1IE — — NCO1IE — — 68 PIE3 — — — — — — CLC2IE CLC1IE 69 PIR1 TMR1GIF ADIF — — — — TMR2IF TMR1IF 70 PIR2 — — C1IF — — NCO1IF — — 71 PIR3
PIC12(L)F1501 NOTES: DS41615A-page 74 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 8.0 POWER-DOWN MODE (SLEEP) The Power-Down mode is entered by executing a SLEEP instruction. Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 7. 8. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep.
PIC12(L)F1501 Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP.
PIC12(L)F1501 8.2 Low-Power Sleep Mode 8.2.2 The PIC12F1501 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC12F1501 allows the user to optimize the operating current in Sleep, depending on the application requirements.
PIC12(L)F1501 VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) REGISTER 8-1: U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 — — — — — — VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode e
PIC12(L)F1501 9.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC12(L)F1501 9.1 Independent Clock Source 9.3 Time-Out Period The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 27.0 “Electrical Specifications” for the LFINTOSC tolerances. The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is 2 seconds. 9.
PIC12(L)F1501 9.
PIC12(L)F1501 TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 OSCCON Bit 6 — PCON Bit 5 Bit 4 Bit 3 IRCF<3:0> STKUNF — RWDT STATUS — — — TO WDTCON — — CONFIG1 Legend: Bit 0 SCS<1:0> RMCLR RI POR PD Z DC WDTPS<4:0> Register on Page 51 BOR 59 C 18 SWDTEN 81 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
PIC12(L)F1501 10.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are: • • • • • • PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software.
PIC12(L)F1501 10.2.1 READING THE FLASH PROGRAM MEMORY FIGURE 10-1: To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data.
PIC12(L)F1501 FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PC +3 PC+3 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here PC + 5 INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(P
PIC12(L)F1501 10.2.2 FLASH MEMORY UNLOCK SEQUENCE FIGURE 10-3: The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing.
PIC12(L)F1501 10.2.3 ERASING FLASH PROGRAM MEMORY FIGURE 10-4: While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 10-2.
PIC12(L)F1501 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2.
PIC12(L)F1501 10.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts.
6 r10 7 - r9 FIGURE 10-5: r8 r7 r6 PMADRH DS41615A-page 90 11 r4 r3 r2 PMADRH<6:0> :PMADRL<7:4> r5 0 7 r1 c3 Preliminary c0 CFGS = 0 PMADRL<4:0> 4 c1 0 CFGS = 1 c2 PMADRL Row Address Decode r0 5 4 0000h 0010h 0020h 7FE0h 000h 001h 002h 7FEh 800h PMDATH 6 8004h - 8005h reserved USER ID 0 - 3 7FF1h 7FE1h 0021h 0011h 0001h Addr 14 Write Latch #1 01h 14 8000h - 8003h 7FF0h Addr 14 Write Latch #0 00h 14 Row 7FFh - 5 0 14 7 14 0 Configuration Words
PIC12(L)F1501 FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config.
PIC12(L)F1501 EXAMPLE 10-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 32 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4.
PIC12(L)F1501 10.3 Modifying Flash Program Memory FIGURE 10-7: When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC12(L)F1501 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 10-2.
PIC12(L)F1501 10.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 10-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM.
PIC12(L)F1501 10.
PIC12(L)F1501 REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1(1) R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 — CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6 C
PIC12(L)F1501 REGISTER 10-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before s
PIC12(L)F1501 11.0 I/O PORTS FIGURE 11-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) Read LATx D Some ports may have one or more of the following additional registers.
PIC12(L)F1501 11.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 11-1. For this device family, the following functions can be moved between different pins. • • • • • These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected.
PIC12(L)F1501 11.2 PORTA Registers 11.2.2 PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 11-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).
PIC12(L)F1501 REGISTER 11-2: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1
PIC12(L)F1501 REGISTER 11-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemented:
PIC12(L)F1501 REGISTER 11-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(3) 1 = Pull-up enabl
PIC12(L)F1501 12.0 INTERRUPT-ON-CHANGE 12.3 The PORTA and PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual port pin, or combination of port pins, can be configured to generate an interrupt.
PIC12(L)F1501 FIGURE 12-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) IOCANx D Q4Q1 Q CK Edge Detect R RAx IOCAPx D Data Bus = 0 or 1 Q Write IOCAFx CK D S Q To Data Bus IOCAFx CK IOCIE R Q2 From all other IOCAFx individual pin detectors Q1 Q2 Q3 Q4 Q4Q1 DS41615A-page 106 Q1 Q1 Q2 Q2 Q3 Q4 Q4Q1 IOC interrupt to CPU core Q3 Q4 Q4 Q4Q1 Preliminary Q4Q1 2011 Microchip Technology Inc.
PIC12(L)F1501 12.
PIC12(L)F1501 TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 INTCON Name GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 107 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 107 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 107 TRISA4 —(1) TRISA2 TRISA1 TR
PIC12(L)F1501 13.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: • ADC input channel • Comparator positive input • Comparator negative input The FVR can be enabled by setting the FVREN bit of the FVRCON register. 13.
PIC12(L)F1501 13.
PIC12(L)F1501 14.0 TEMPERATURE INDICATOR MODULE FIGURE 14-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC12(L)F1501 TABLE 14-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 118 Shaded cells are unused by the temperature indicator module. DS41615A-page 112 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 15.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC12(L)F1501 15.1 ADC Configuration 15.1.4 When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 15.1.1 The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 11.
PIC12(L)F1501 TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 (2) 200 ns (2) 250 ns (2) FOSC/8 001 400 ns(2) 0.5 s(2) FOSC/16 101 800 ns 1.0 s FOSC/32 1.6 s 010 2.0 s FOSC/64 110 3.2 s 4.0 s FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Legend: Note 1: 2: 3: 4: 1.
PIC12(L)F1501 15.1.5 INTERRUPTS 15.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC12(L)F1501 15.2 15.2.1 ADC Operation 15.2.4 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 15.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 15.2.6 “A/D Conversion Procedure”.
PIC12(L)F1501 15.2.6 A/D CONVERSION PROCEDURE EXAMPLE 15-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC12(L)F1501 15.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC12(L)F1501 REGISTER 15-2: R/W-0/0 ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 — — R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified.
PIC12(L)F1501 REGISTER 15-3: R/W-0/0 ADCON2: A/D CONTROL REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 TRIGSEL<3:0> U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1) 0000 = No auto-conversion trigger selected 0001 = Reserved 0010 = Reserv
PIC12(L)F1501 REGISTER 15-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 15-5: R/W-x/u ADRE
PIC12(L)F1501 REGISTER 15-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
PIC12(L)F1501 15.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 15-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 15-4.
PIC12(L)F1501 FIGURE 15-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.
PIC12(L)F1501 TABLE 15-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 — ADCON1 ADFM ADCON2 Bit 6 Bit 5 Bit 4 Bit 2 — — ADPREF<1:0> 120 — — — 121 CHS<4:0> ADCS<2:0> TRIGSEL<3:0> Bit 1 Bit 0 GO/DONE ADON Register on Page Bit 3 — 119 ADRESH A/D Result Register High 122, 123 ADRESL A/D Result Register Low 122, 123 ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66 PIE1 TMR1GIE ADIE — — — —
PIC12(L)F1501 16.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The input of the DAC can be connected to: 16.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register.
PIC12(L)F1501 FIGURE 16-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) VSOURCE+ VDD DACR<4:0> 5 VREF+ R R DACPSS R DACEN R 32 Steps R 32-to-1 MUX R DAC (To Comparator and ADC Module) R DACOUT1 R DACOE1 VSOURCE- DACOUT2 DACOE2 FIGURE 16-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS41615A-page 128 DACOUTX Preliminary + – Buffered DAC Output 2011 Microchip Technology Inc.
PIC12(L)F1501 16.4 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 16.5 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. 2011 Microchip Technology Inc.
PIC12(L)F1501 16.
PIC12(L)F1501 17.0 COMPARATOR MODULE FIGURE 17-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
PIC12(L)F1501 FIGURE 17-2: COMPARATOR MODULES SIMPLIFIED BLOCK DIAGRAM CxNCH<2:0> CxON(1) 3 C12IN0- 0 C12IN1C12IN2- 1 MUX 2 (2) C12IN3- 3 FVR Buffer2 4 det Set CxIF 0 MUX 1 (2) DAC FVR Buffer2 CxINTN Interrupt det CXPOL CxVN D Cx CxVP CXIN+ CxINTP Interrupt CXOUT MCXOUT Q To Data Bus + EN Q1 CxHYS CxSP async_CxOUT To CWG 2 3 CXSYNC CxON CXPCH<1:0> CXOE TRIS bit CXOUT 0 2 D (from Timer1) T1CLK Note 1: 2: Q 1 SYNC_CXOUT To Timer1, CLCx, ADC When CxON = 0, the comparato
PIC12(L)F1501 17.2 Comparator Control 17.2.3 Each comparator has 2 control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 17-1) contain Control and Status bits for the following: • • • • • • Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs.
PIC12(L)F1501 17.3 Comparator Hysteresis 17.5 A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. See Section 27.
PIC12(L)F1501 17.7 Comparator Negative Input Selection 17.9 The CxNCH<1:0> bits of the CMxCON0 register direct one of the input sources to the comparator inverting input. Note: 17.8 To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers.
PIC12(L)F1501 FIGURE 17-3: ANALOG INPUT MODEL VDD Rs < 10K Analog Input pin VT 0.6V RIC To Comparator VA CPIN 5 pF VT 0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS = Analog Voltage VA = Threshold Voltage VT Note 1: DS41615A-page 136 See Section 27.0 “Electrical Specifications”. Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 REGISTER 17-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled and consumes no active power 0
PIC12(L)F1501 REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 CxPCH<1:0> U-0 R/W-0/0 R/W-0/0 R/W-0/0 CxNCH<2:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt fl
PIC12(L)F1501 TABLE 17-3: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 C1OE C1POL — C1SP C1HYS C1SYNC 137 CM1CON0 C1ON C1OUT CM1CON1 C1NTP C1INTN — — — — — — — MC1OUT 138 DACEN — DACOE1 DACOE2 — DACPSS — — 130 CDAFVR<1:0> CMOUT DACCON0 C1PCH<1:0> — C1NCH<2:0> 138 — — — FVRCON FVREN FVRRDY TSEN TSRNG INTCON GIE PEIE TMR0
PIC12(L)F1501 NOTES: DS41615A-page 140 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 18.0 TIMER0 MODULE 18.1.2 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. • • • • • • 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘1’.
PIC12(L)F1501 18.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC12(L)F1501 18.
PIC12(L)F1501 NOTES: DS41615A-page 144 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 19.0 TIMER1 MODULE WITH GATE CONTROL • Gate Single-Pulse mode • Gate Value Status • Gate Event Interrupt The Timer1 module is a 16-bit timer/counter with the following features: Figure 19-1 is a block diagram of the Timer1 module.
PIC12(L)F1501 19.1 Timer1 Operation 19.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.
PIC12(L)F1501 19.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 19.4 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized.
PIC12(L)F1501 19.5.2.1 T1G Pin Gate Operation 19.5.5 The T1G pin is one source for Timer1 Gate Control. It can be used to supply an external source to the Timer1 gate circuitry. 19.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 19.5.
PIC12(L)F1501 19.6 Timer1 Interrupt 19.7.1 The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set.
PIC12(L)F1501 FIGURE 19-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 19-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 DS41615A-page 150 N N+1 N+2 N+3 N+4 Preliminary N+5 N+6 N+7 N+8 2011 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 19-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N N+1 Set by hardware on falling edge of T1GVAL Cleared by software 2011 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 19-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS41615A-page 152 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL Preliminary N+4 Cleared by software 2011 Microchip Technology Inc.
PIC12(L)F1501 19.
PIC12(L)F1501 REGISTER 19-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If T
PIC12(L)F1501 19.8.1 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 11.1 “Alternate Pin Function” for more information.
PIC12(L)F1501 NOTES: DS41615A-page 156 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 20.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively See Figure 20-1 for a block diagram of Timer2.
PIC12(L)F1501 20.1 Timer2 Operation 20.3 The clock input to the Timer2 module is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle.
PIC12(L)F1501 REGISTER 20-1: U-0 T2CON: TIMER2 CONTROL REGISTER R/W-0/0 — R/W-0/0 R/W-0/0 R/W-0/0 T2OUTPS<3:0> R/W-0/0 R/W-0/0 TMR2ON bit 7 R/W-0/0 T2CKPS<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscal
PIC12(L)F1501 TABLE 20-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66 PIE1 TMR1GIE ADIE — — — — TMR2IE TMR1IE 67 PIR1 TMR1GIF ADIF — — — — TMR2IF TMR1IF PR2 Timer2 Module Period Register 70 157* PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL — — — — 165 PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL — — — — 165 PWM3CON PWM3EN PWM3OE PWM3OUT
PIC12(L)F1501 21.0 PULSE-WIDTH MODULATION (PWM) MODULE For a step-by-step procedure on how to set up this module for PWM operation, refer to Section 21.1.9 “Setup for PWM Operation using PWMx Pins”.
PIC12(L)F1501 21.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. Note: 21.1.1 Clearing the PWMxOE bit will relinquish control of the PWMx pin. FUNDAMENTAL OPERATION The PWM module produces a 10-bit resolution output. Timer2 and PR2 set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle.
PIC12(L)F1501 21.1.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 21-4.
PIC12(L)F1501 21.1.9 SETUP FOR PWM OPERATION USING PWMx PINS The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). 2. Clear the PWMxCON register. 3. Load the PR2 register with the PWM period value. 4. Clear the PWMxDCH register and bits <7:6> of the PWMxDCL register. 5. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note below.
PIC12(L)F1501 21.
PIC12(L)F1501 REGISTER 21-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWMxDCH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle.
PIC12(L)F1501 22.0 CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLC) provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 16 input signals and through the use of configurable gates reduces the 16 inputs to four logic lines that drive one of eight selectable single-output logic functions.
PIC12(L)F1501 22.1 CLCx Setup 22.1.1 Programming the CLCx module is performed by configuring the 4 stages in the logic signal flow. The 4 stages are: • • • • Data selection Data gating Logic function selection Output polarity Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution.
PIC12(L)F1501 22.1.2 DATA GATING Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. Note: 22.1.3 Data gating is undefined at power-up. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. Directed signals are ANDed together in each gate.
PIC12(L)F1501 22.1.5 CLCx SETUP STEPS The following steps should be followed when setting up the CLCx: • Disable CLCx by clearing the LCxEN bit. • Select desired inputs using CLCxSEL0 and CLCxSEL1 registers (See Table 22-1). • Clear any associated ANSEL bits. • Set all TRIS bits associated with inputs. • Clear all TRIS bits associated with outputs. • Enable the chosen inputs through the four gates using CLCxGLS0, CLCxGLS1, CLCxGLS2, and CLCxGLS3 registers.
PIC12(L)F1501 FIGURE 22-2: CLCxIN[0] CLCxIN[1] CLCxIN[2] CLCxIN[3] CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] INPUT DATA SELECTION AND GATING Data Selection 000 Data GATE 1 lcxd1T LCxD1G1T lcxd1N LCxD1G1N 111 LCxD2G1T LCxD1S<2:0> LCxD2G1N CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] CLCxIN[8] CLCxIN[9] CLCxIN[10] CLCxIN[11] LCxD3G1T lcxd2T LCxD3G1N LCxD4G1T 111 LCxD4G1N 000 Data GATE 2 lcxg2 lcxd3T (Same as Data GATE 1) lcxd3N Data GATE 3 111 lcxg3 LCxD3S<2:0> CLCxIN[12] CLCxIN[13] CLCxIN[14] C
PIC12(L)F1501 FIGURE 22-3: PROGRAMMABLE LOGIC FUNCTIONS AND - OR OR - XOR lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxg3 lcxq lcxg3 lcxg4 lcxg4 LCxMODE<2:0>= 000 LCxMODE<2:0>= 001 4-Input AND S-R Latch lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxg3 S lcxg3 lcxg4 R lcxg4 LCxMODE<2:0>= 010 lcxq Q LCxMODE<2:0>= 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 lcxg2 D S lcxg4 Q lcxq D lcxg2 lcxg1 lcxg1 Q lcxq R R lcxg3 lcxg3 LCxMODE<2:0>= 100 LCxMODE<2:0>= 101 J-K Fli
PIC12(L)F1501 22.
PIC12(L)F1501 REGISTER 22-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxPOL: LCOUT Polarity Control bit 1 = The output of the logic cell is inverted 0 =
PIC12(L)F1501 REGISTER 22-3: U-0 CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER R/W-x/u — R/W-x/u R/W-x/u LCxD2S<2:0> U-0 — R/W-x/u R/W-x/u R/W-x/u LCxD1S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 LCxD2S<2:0>: Input Data 2 Selection Control bits(1) 111 = CL
PIC12(L)F1501 REGISTER 22-4: U-0 CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER R/W-x/u — R/W-x/u R/W-x/u LCxD4S<2:0> U-0 — R/W-x/u R/W-x/u R/W-x/u LCxD3S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 LCxD4S<2:0>: Input Data 4 Selection Control bits(1) 111 = CL
PIC12(L)F1501 REGISTER 22-5: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit 1 =
PIC12(L)F1501 REGISTER 22-6: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit 1 =
PIC12(L)F1501 REGISTER 22-7: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit 1 =
PIC12(L)F1501 REGISTER 22-8: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit 1 =
PIC12(L)F1501 REGISTER 22-9: CLCDATA: CLC DATA OUTPUT U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0 — — — — — — MLC2OUT MLC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit 2011 Microchip Technolo
PIC12(L)F1501 TABLE 22-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 — Bit1 Bit0 Register on Page CLC1SEL NCO1SEL 100 — — T1GSEL CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN CLC2CON LC2EN LC2OE LC2OUT LC2INTP LC2INTN CLCDATA — — — — — — MLC2OUT MLC1OUT 177 CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 177 CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N
PIC12(L)F1501 23.0 NUMERICALLY CONTROLLED OSCILLATOR (NCO) MODULE The Numerically Controlled Oscillator (NCOx) module is a timer that uses the overflow from the addition of an increment value to divide the input frequency. The advantage of the addition method over simple counter driven timer is that the resolution of division does not vary with the divider value. The NCOx is most useful for applications that require frequency accuracy and fine resolution at a fixed duty cycle.
DS41615A-page 184 Preliminary Note 1: 2 NxEN NxCKS<2:0> 00 01 10 11 20 (1) NCOx Clock 20 Accumulator 16 Buffer 16 Increment Ripple Counter NCOx Clock Overflow Q Q R Q Q S NxPWS<2:0> Reset 3 Overflow D Interrupt event NxPOL NxPFM 1 0 NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM The increment registers are double-buffered to allow for value changes to be made without first disabling the NCOx module. They are shown here for reference.
PIC12(L)F1501 23.1 NCOx OPERATION 23.1.3 ADDER The NCOx operates by repeatedly adding a fixed value to an accumulator. Additions occur at the input clock rate. The accumulator will overflow with a carry periodically, which is the raw NCOx output. This effectively reduces the input clock by the ratio of the addition value to the maximum accumulator value. See Equation 23-1. The NCOx Adder is a full adder, which operates independently from the system clock.
PIC12(L)F1501 23.2 FIXED DUTY CYCLE (FDC) MODE In Fixed Duty Cycle (FDC) mode, every time the accumulator overflows, the output is toggled. This provides a 50% duty cycle, provided that the increment value remains constant. For more information, see Figure 23-2. The FDC mode is selected by clearing the NxPFM bit in the NCOxCON register. 23.3 PULSE FREQUENCY (PF) MODE In Pulse Frequency (PF) mode, every time the accumulator overflows, the output becomes active for one or more clock periods.
DS41615A-page 187 Preliminary NCOx Output PF mode NCOx PWS = 010 NCOx Output PF mode NCOX PWS = 000 NCOx Output FDC mode Interrupt Event Overflow PWS = 000 NCOx Accumulator Value Accumulator Input Overflow NCOx Accumulator Input NCOx Increment Value 0000h 02000h 2000h 04000h 4000h 06000h 6000h 08000h 0C000h Tadder 0E000h 8000h A000h C000h Overflow is the MSB of the accumulator 0A000h FDC OUTPUT MODE OPERATION DIAGRAM Clock Source FIGURE 23-2: E000h 10000h Tadder 0000h Tadder
PIC12(L)F1501 23.5 Interrupts When the accumulator overflows, the NCOx Interrupt Flag bit, NCOxIF, of the PIRx register is set. To enable the interrupt event, the following bits must be set: • • • • NxEN bit of the NCOxCON register NCOxIE bit of the PIEx register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt must be cleared by software by clearing the NCOxIF bit in the Interrupt Service Routine. 23.
PIC12(L)F1501 23.
PIC12(L)F1501 REGISTER 23-3: R/W-0/0 NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxACC<7:0>: NCOx Accumulator, low byte REGISTER 23-4: R/W-0/0 NCOxACCH: NCOx ACCUMULATOR REGISTER – HIGH
PIC12(L)F1501 REGISTER 23-6: R/W-0/0 NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 NCOxINC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxINC<7:0>: NCOx Increment, low byte REGISTER 23-7: R/W-0/0 NCOxINCH: NCOx INCREMENT REGISTER – HIGH BYTE
PIC12(L)F1501 TABLE 23-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH NCOx Bit 7 APFCON Bit 6 CWG1BSEL CWG1ASEL INTCON GIE PEIE Bit 2 Bit 1 Bit 0 Register on Page T1GSEL — CLC1SEL NCO1SEL 100 IOCIE TMR0IF INTF IOCIF 66 Bit 5 Bit 4 Bit 3 — — TMR0IE INTE NCO1ACCH NCO1ACC<15:8> 190 NCO1ACCL NCO1ACC<7:0> 190 — NCO1ACCU NCO1CLK NCO1CON NCO1ACC<19:16> N1PWS<2:0> N1EN N1OE N1OUT NCO1INCH — — — N1POL — — 190 N1CKS<1:0> — N1PFM NCO1INC<15:8> NCO1INCL 189 189 191 NC
PIC12(L)F1501 24.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band delay from a selection of input sources.
2011 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 24-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN) cwg_clock PWM1 CWGxA Rising Edge Dead Band Falling Edge Dead Band Rising Edge Dead Band Rising Edge D Falling Edge Dead Band CWGxB 2011 Microchip Technology Inc.
PIC12(L)F1501 24.1 Fundamental Operation 24.4.2 The CWG generates a two output complementary waveform from one of four selectable input sources. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time delay immediately where neither output is driven. This is referred to as dead time and is covered in Section 24.5 “Dead-Band Control”.
PIC12(L)F1501 24.7 Falling Edge Dead Band The falling edge dead band delays the turn-on of the CWGxB output from when the CWGxA output is turned off. The falling edge dead-band time starts when the falling edge of the input source goes true. When this happens, the CWGxA output is immediately turned off and the falling edge dead-band delay time starts. When the falling edge dead-band delay time is reached, the CWGxB output is turned on.
2011 Microchip Technology Inc.
PIC12(L)F1501 EQUATION 24-1: DEAD-BAND UNCERTAINTY 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock Example: Fcwg_clock = 16 MHz Therefore: 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock 1 = ------------------16 MHz = 625ns 2011 Microchip Technology Inc.
PIC12(L)F1501 24.9 Auto-shutdown Control 24.10 Operation During Sleep Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. 24.9.1 SHUTDOWN The shutdown state can be entered by either of the following two methods: • Software generated • External Input 24.9.1.
PIC12(L)F1501 24.12 Configuring the CWG 24.12.1 The following steps illustrate how to properly configure the CWG to ensure a synchronous start: The levels driven to the output pins, while the shutdown input is true, are controlled by the GxASDLA and GxASDLB bits of the CWGxCON2 register (Register 24-3). GxASDLA controls the CWG1A override level and GxASDLB controls the CWG1B override level. The control bit logic level corresponds to the output logic drive level while in the shutdown state.
2011 Microchip Technology Inc.
PIC12(L)F1501 24.
PIC12(L)F1501 REGISTER 24-2: R/W-x/u CWGxCON1: CWG CONTROL REGISTER 1 R/W-x/u GxASDLB<1:0> R/W-x/u R/W-x/u U-0 GxASDLA<1:0> — R/W-0/0 R/W-0/0 R/W-0/0 GxIS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 GxASDLB<1:0>: CWGx Shutdown State for CWGxB When an auto shutdown
PIC12(L)F1501 REGISTER 24-3: CWGxCON2: CWG CONTROL REGISTER 2 R/W-0/0 R/W-0/0 G1ASE G1ARSEN U-0 — U-0 — U-0 R/W-0/0 R/W-0/0 R/W-0/0 — G1ASDC1 G1ASDFLT G1ASDCLC2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 G1ASE: Auto-Shutdown Event Status bit 1 = An auto-shutdown event
PIC12(L)F1501 REGISTER 24-4: U-0 CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING DEAD-BAND COUNT REGISTER U-0 — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CWGxDBR<5:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CWGxDBR<
PIC12(L)F1501 24.13.1 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 11.1 “Alternate Pin Function” for more information.
PIC12(L)F1501 NOTES: DS41615A-page 208 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 25.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) 25.3 ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS Connection to a target device is typically done through an ICSP™ header.
PIC12(L)F1501 FIGURE 25-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins. For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry.
PIC12(L)F1501 26.0 INSTRUCTION SET SUMMARY 26.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC12(L)F1501 FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal)
PIC12(L)F1501 TABLE 26-3: PIC12(L)F1501 ENHANCED INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clea
PIC12(L)F1501 TABLE 26-3: PIC12(L)F1501 ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS 2 2 2 2 2 2 2 2 BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation
PIC12(L)F1501 26.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND.
PIC12(L)F1501 BCF Bit Clear f Syntax: [ label ] BCF f,b BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC12(L)F1501 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC12(L)F1501 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC12(L)F1501 LSLF Logical Left Shift f {,d} MOVF Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC12(L)F1501 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) • Unchanged Status Affected: MOVLP Move literal to PCLAT
PIC12(L)F1501 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged None Mode Syntax mm Preincre
PIC12(L)F1501 RETFIE Return from Interrupt Syntax: [ label ] RETURN RETFIE k Return from Subroutine Syntax: [ label ] None RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC12(L)F1501 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
PIC12(L)F1501 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: SWAPF f,d (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC12(L)F1501 27.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC12F1501 ............................................................................. -0.
PIC12(L)F1501 PIC12F1501 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 27-1: VDD (V) 5.5 2.5 2.3 4 0 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 27-1 for each Oscillator mode’s supported frequencies. PIC12LF1501 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 27-2: 3.6 2.5 1.
PIC12(L)F1501 27.1 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended) PIC12LF1501 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1501 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym. VDD Characteristic VDR Units Conditions PIC12LF1501 1.8 2.5 — — 3.6 3.
PIC12(L)F1501 FIGURE 27-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: DS41615A-page 228 TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 27.2 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended) PIC12LF1501 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1501 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max. Units — 25 140 A 1.8 — 45 230 A 3.
PIC12(L)F1501 27.2 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended) (Continued) PIC12LF1501 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1501 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max. Units — 34 210 A 3.
PIC12(L)F1501 27.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down) PIC12LF1501 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1501 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Power-down Base Current D022 D022 D023 D023 D023A D023A Conditions Typ† Max.
PIC12(L)F1501 27.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down) (Continued) PIC12LF1501 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1501 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Max. +85°C Max. +125°C Units — 20 43 55 A 1.
PIC12(L)F1501 27.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down) (Continued) PIC12LF1501 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1501 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Typ† Max.
PIC12(L)F1501 27.4 DC Characteristics: PIC12(L)F1501-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR VIH — — 0.8 V 4.5V VDD 5.5V — — 0.15 VDD V 1.8V VDD 4.5V — — 0.2 VDD V 2.0V VDD 5.
PIC12(L)F1501 27.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA D112 VBE VDD for Bulk Erase 2.7 — VDD max. V D113 VPEW VDD for Write or Row Erase VDD min. — VDD max.
PIC12(L)F1501 27.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 89.3 C/W 8-pin PDIP package 149.5 C/W 8-pin SOIC package 211 C/W 8-pin MSOP package 56.
PIC12(L)F1501 27.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC12(L)F1501 27.8 AC Characteristics: PIC12(L)F1501-I/E FIGURE 27-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS12 OS02 OS11 OS03 CLKOUT (CLKOUT Mode) Note 1: See Table 27-3. TABLE 27-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. Typ† Max. Units Conditions DC — 0.
PIC12(L)F1501 FIGURE 27-6: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 27-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS11 OS12 Sym. TosH2ckL Characteristic Min. Typ† Max.
PIC12(L)F1501 FIGURE 27-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 27-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’.
PIC12(L)F1501 TABLE 27-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 10 16 27 ms VDD = 3.
PIC12(L)F1501 TABLE 27-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. 40* Sym. Characteristic TT0H T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler — — ns — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns 0.
PIC12(L)F1501 TABLE 27-7: PIC12(L)F1501 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym. Characteristic AD130* TAD AD131 TCNV AD132* TACQ Min. Typ† Max. Units Conditions A/D Clock Period 1.0 — 9.0 s TOSC-based A/D Internal FRC Oscillator Period 1.0 1.6 6.
PIC12(L)F1501 FIGURE 27-11: PIC12(L)F1501 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK 9 A/D Data 8 7 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample AD132 Sampling Stopped Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. DS41615A-page 244 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 TABLE 27-8: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param No. Sym. Characteristics Typ. Max. Units — ±7.
PIC12(L)F1501 NOTES: DS41615A-page 246 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 28.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. 2011 Microchip Technology Inc.
PIC12(L)F1501 NOTES: DS41615A-page 248 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 29.0 DEVELOPMENT SUPPORT 29.
PIC12(L)F1501 29.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 29.
PIC12(L)F1501 29.7 MPLAB SIM Software Simulator 29.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC12(L)F1501 29.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 29.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC12(L)F1501 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 8-Lead PDIP (300 mil) Example 12F1501 I/P e3 017 1110 XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (3.90 mm) Example 12F1501 I/SN1110 017 NNN Legend: XX...
PIC12(L)F1501 Package Marking Information (Continued) 8-Lead MSOP (3x3 mm) Example F1501I 110017 8-Lead DFN (2x3x0.9 mm) Example BAK 110 10 8-Lead DFN (3x3x0.9 mm) Example XXXX YYWW NNN MFB1 1110 017 PIN 1 DS41615A-page 254 PIN 1 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 TABLE 30-1: 8-LEAD 2x3 DFN (MC) TOP MARKING Part Number PIC12F1501-E/MC Marking BAK PIC12F1501-I/MC BAL PIC12LF1501-E/MC BAM PIC12LF1501-I/MC BAP TABLE 30-2: 8-LEAD 3x3 QFN (MF) TOP MARKING Part Number PIC12F1501-E/MF Marking MFA1 PIC12F1501-I/MF MFB1 PIC12LF1501-E/MF MFC1 PIC12LF1501-I/MF MFD1 2011 Microchip Technology Inc.
PIC12(L)F1501 30.2 Package Details The following sections give the technical details of the packages. 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6 &! ' ! 9 ' &! 7"') % ! 7,8.
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41615A-page 258 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 ! "" #$ %& ! ' 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 2011 Microchip Technology Inc.
PIC12(L)F1501 ( " ! ) * ( ( ! 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; < & : 8 & = = < = # # 4 4 !! & # %% ? 1 , : > #& . # # 4 > #& .
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC12(L)F1501 + $ ) * (' ,- - %& + 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D e b N N L K E2 E EXPOSED PAD NOTE 1 2 1 NOTE 1 1 2 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 6 &! ' ! 9 ' &! 7"') % ! 99 . .
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41615A-page 264 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41615A-page 266 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 APPENDIX A: DATA SHEET REVISION HISTORY Revision A Original release (11/2011). 2011 Microchip Technology Inc.
PIC12(L)F1501 NOTES: DS41615A-page 268 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 INDEX A A/D Specifications.................................................... 242, 243 Absolute Maximum Ratings .............................................. 225 AC Characteristics Industrial and Extended ............................................ 238 Load Conditions ........................................................ 237 ADC .................................................................................. 113 Acquisition Requirements .........................................
PIC12(L)F1501 Auto-shutdown Control ............................................. 200 Clock Source............................................................. 196 Output Control........................................................... 196 Selectable Input Sources .......................................... 196 CWGxCON0 Register ....................................................... 203 CWGxCON1 Register ....................................................... 204 CWGxCON2 Register ........................
PIC12(L)F1501 M MCLR .................................................................................. 56 Internal ........................................................................ 56 Memory Organization.......................................................... 15 Data ............................................................................ 17 Program ...................................................................... 15 Microchip Internet Web Site ............................................
PIC12(L)F1501 Configuration Word 2 .................................................. 41 Core Function, Summary ............................................ 24 CWGxCON0 (CWG Control 0).................................. 203 CWGxCON1 (CWG Control 1).................................. 204 CWGxCON2 (CWG Control 1).................................. 205 CWGxDBF (CWGx Dead Band Falling Count) ......... 206 CWGxDBR (CWGx Dead Band Rising Count) ......... 206 DACCON0 ..................................................
PIC12(L)F1501 V VREF. SEE ADC Reference Voltage VREGCON Register ........................................................... 78 W Wake-up Using Interrupts ................................................... 75 Watchdog Timer (WDT) ...................................................... 56 Associated Registers .................................................. 82 Modes ......................................................................... 80 Specifications..................................................
PIC12(L)F1501 NOTES: DS41615A-page 274 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1501 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC12(L)F1501 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
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