Datasheet

PIC12C67X
DS30561C-page 58  1997-2013 Microchip Technology Inc.
9.4 Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
9.4.1 POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in reset until
V
DD has reached a high enough level for proper opera-
tion. To take advantage of the POR, just tie the MCLR
pin through a resistor to VDD. This will eliminate exter-
nal RC components usually needed to create a Power-
on Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, "
Power-up Trouble Shooting ."
9.4.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT’s time delay allows V
DD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
The power-up time delay will vary from chip to chip due
to V
DD, temperature and process variation. See
Table 11-4.
9.4.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscil-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
9.4.4 TIME-OUT SEQUENCE
On power-up, the Time-out Sequence is as follows:
first, PWRT time-out is invoked after the POR time
delay has expired; then, OST is activated. The total
time-out will vary, based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 9-7, Figure 9-8, and Figure 9-9 depict time-out
sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR
high will begin execution immediately
(Figure 9-9). This is useful for testing purposes or to
synchronize more than one PIC12C67X device operat-
ing in parallel.
9.4.5 POWER CONTROL (PCON)/STATUS
REGISTER
The Power Control/Status Register, PCON (address
8Eh), has one bit. See Register 4-6 for register.
Bit1 is POR
(Power-on Reset). It is cleared on a Power-
on Reset and is unaffected otherwise. The user sets
this bit following a Power-on Reset. On subsequent
resets, if POR is ‘0’, it will indicate that a Power-on
Reset must have occurred.
TABLE 9-4: TIME-OUT IN VARIOUS SITUATIONS
TABLE 9-5: STATUS/PCON BITS AND THEIR SIGNIFICANCE
Legend: u = unchanged, x = unknown.
Oscillator Configuration Power-up Wake-up from SLEEP
PWRTE
= 0 PWRTE = 1
XT, HS, LP 72 ms + 1024T
OSC 1024TOSC 1024TOSC
INTRC, EXTRC 72 ms — —
POR
TO PD
011Power-on Reset
00xIllegal, TO
is set on POR
0x0Illegal, PD is set on POR
10uWDT Reset
100WDT Wake-up
1uuMCLR
Reset during normal operation
110MCLR Reset during SLEEP or interrupt wake-up from SLEEP