Information
2001 Microchip Technology Inc. DS80068C-page 5
PIC12CE67X
2. Module: OSCCAL Register
Correction for the “OSCCAL” Register, Section 4.2.2.7,
is shown.
4.2.2.7
OSCCAL REGISTER
The Oscillator Calibration (OSCCAL) Register is
used to calibrate the internal 4 MHz oscillator. It
contains six bits for calibration. Increasing the
value increases the frequency.
REGISTER 4-7: OSCCAL REGISTER (ADDRESS 8Fh)
3. Module: GPIO Register
Clarification to the “GPIO”, Section 5.1 is provided.
New I/O drawings were added.
5.1 GPIO
GPIO is an 8-bit I/O register. Only the low order 6
bits are used (GP<5:0>). Bits 6 and 7 (SDA and
SCL, respectively) are used by the EEPROM
peripheral on the PIC12CE673/674. Refer to Sec-
tion 6.0 and Appendix B for use of SDA and SCL.
Please note that GP3 is an input only pin. The con-
figuration word can set several I/O’s to alternate
functions. When acting as alternate functions, the
pins will read as ‘0’ during port read.
Pins GP0, GP1 and GP3 can be configured with
weak pull-ups and also with interrupt-on-change.
The interrupt on change and weak pull-up func-
tions are not pin selectable. If pin 4, (GP3), is con-
figured as MCLR
, a weak pull-up is always on.
Interrupt-on-change for this pin is not set and GP3
will read as '0'. Interrupt-on-change is enabled by
setting bit GPIE, INTCON<3>.
The interrupt can wake the device from SLEEP.
The user, in the interrupt service routine, can clear
the interrupt in the following manner:
a) Any read or write of GPIO will end the mis-
match condition.
b) Clear flag bit GPIF.
A mismatch condition will continue to set flag bit
GPIF. Reading GPIO will end the mismatch condi-
tion and allow flag bit GPIF to be cleared.
Note that external oscillator use overrides the
GPIO functions on GP4 and GP5.
FIGURE 5-1: GP0 and GP1 Block Diagram
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
— —
bit 7 bit 0
bit 7-2 CAL<5:0>: Calibration
bit 1-0 Unimplemented: Read as ’0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
EN
Q
D
EN
Q
Analog
Input
Mode
Data bus
RD PORT
RD
PORT
WR
PORT
WR
TRIS
RD
TRIS
To A/D Converter
GPPU
VDD
Weak
Interrupt-on-Change