Information

PIC12CE67X

DS80068C-page 4  2001 Microchip Technology Inc.

Clarifications/Corrections to the Data Sheet:

In the Device Data Sheet (DS30561B), the following

clarifications and corrections should be noted.

1. Module: Register Summary (OSCCAL)

In Section 4.0, corrections for the Special Function

TABLE 4-1: PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

all other

RESETS

(3)

Bank 1

8Fh OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

— — 1000 00-- uuuu uu--

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

3: Other (non Power-up) Resets include external RESET through MCLR

and Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved on the PIC12CE67X; always maintain these bits clear.

5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.