Datasheet

 1997-2013 Microchip Technology Inc. DS30561C-page 35
PIC12C67X
FIGURE 6-3: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 6-4: ACKNOWLEDGE TIMING
6.2 Device Addressing
After generating a START condition, the processor
transmits a control byte consisting of a EEPROM
address and a Read/Write bit that indicates what type
of operation is to be performed. The EEPROM address
consists of a 4-bit device code (1010) followed by three
don't care bits.
The last bit of the control byte determines the operation
to be performed. When set to a one, a read operation
is selected, and when set to a zero, a write operation is
selected (Figure 6-5). The bus is monitored for its cor-
responding EEPROM address all the time. It generates
an acknowledge bit if the EEPROM address was true
and it is not in a programming mode.
FIGURE 6-5: CONTROL BYTE FORMAT
(A) (B) (C) (D) (A)(C)
SCL
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VAL ID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SCL
987654321 123
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
Data from transmitter
Data from transmitter
SDA
Acknowledge
Bit
1010XXXSACKR/W
Device Select
Bits
Don’t Care
Bits
EEPROM Address
Acknowledge Condition
Start Condition
Read/Write
Bit