Datasheet

PIC12C67X
DS30561C-page 48  1997-2013 Microchip Technology Inc.
8.1 A/D Sampling Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
HOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 8-2. The source
impedance (R
S) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (V
DD), see
Figure 8-2. The maximum recommended imped-
ance for analog sources is 10 k. After the analog
input channel is selected (changed), this acquisition
must be done before the conversion can be started.
To calculate the minimum acquisition time, Equation 8-1
may be used. This equation assumes that 1/2 LSb error
is used (512 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.
EQUATION 8-1: A/D MINIMUM CHARGING
TIME
VHOLD = (VREF - (VREF/512)) • (1 - e
(-Tc/CHOLD(RIC + RSS + RS))
)
or
Tc = -(51.2 pF)(1 k + R
SS + RS) ln(1/511)
Example 8-1 shows the calculation of the minimum
required acquisition time T
ACQ. This calculation is
based on the following system assumptions.
Rs = 10 k

1/2 LSb error
V
DD = 5V  Rss = 7 k
Temp (system max.) = 50C
V
HOLD = 0 @ t = 0
EXAMPLE 8-1: CALCULATING THE
MINIMUM REQUIRED
SAMPLE TIME
TACQ = Internal Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
T
ACQ =5 s + Tc + [(Temp - 25C)(0.05 s/C)]
T
C =-CHOLD (RIC + RSS + RS) ln(1/512)
-51.2 pF (1 k + 7 k + 10 k) ln(0.0020)
-51.2 pF (18 k) ln(0.0020)
-0.921 s (-6.2146)
5.724 s
T
ACQ =5 s + 5.724 s + [(50C - 25C)(0.05 s/C)]
10.724 s + 1.25 s
11.974 s
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
2: The charge holding capacitor (C
HOLD) is
not discharged after each conversion.
3: The maximum recommended impedance
for analog sources is 10 k. This is
required to meet the pin leakage specifi-
cation.
4: After a conversion has completed, a
2.0 T
AD delay must complete before
acquisition can begin again. During this
time, the holding capacitor is not con-
nected to the selected A/D input channel.
FIGURE 8-2: ANALOG INPUT MODEL
CPIN
VA
Rs
RAx
5 pF
V
DD
VT = 0.6V
V
T = 0.6V
I leakage
R
IC 1k
Sampling
Switch
SS
Rss
C
HOLD
= DAC capacitance
V
SS
6V
Sampling Switch
5V
4V
3V
2V
567891011
( k )
VDD
= 51.2 pF
± 500 nA
Legend: CPIN
VT
I leakage
R
IC
SS
C
HOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions