Datasheet

 1997-2013 Microchip Technology Inc. DS30561C-page 41
PIC12C67X
7.2 Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T
OSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1 EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
used as the clock source. The synchronization of
T0CKI with the internal phase clocks is accomplished
by sampling the prescaler output on the Q2 and Q4
cycles of the internal phase clocks (Figure 7-5). There-
fore, it is necessary for T0CKI to be high for at least
2T
OSC (and a small RC delay of 20 ns) and low for at
least 2T
OSC (and a small RC delay of 20 ns). Refer to
the electrical specification of the desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type pres-
caler, so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple-counter must be taken into account. There-
fore, it is necessary for T0CKI to have a period of at
least 4T
OSC (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the mini-
mum pulse width requirement of 10 ns. Refer to param-
eters 40, 41 and 42 in the electrical specification of the
desired device.
7.2.2 TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 mod-
ule is actually incremented. Figure 7-5 shows the delay
from the external clock edge to the timer incrementing.
FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
External Clock Input or
Prescaler output
(2)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0 T0 + 1 T0 + 2
Small pulse
misses sampling
(3)
(1)
Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4T
OSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.