Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PDIP 8 8-Bit 10 MHz I/O number 5

 1997-2013 Microchip Technology Inc. DS30561C-page 13

PIC12C67X

TABLE 4-1: PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

all other

Resets

(3)

Bank 0

00h

(1)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

03h

(1)

STATUS IRP

(4)

RP1

(4)

RP0 TO PD ZDCC0001 1xxx 000q quuu

04h

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

05h GPIO SCL

(5)

SDA

(5)

GP5 GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu

06h — Unimplemented — —

07h — Unimplemented — —

08h — Unimplemented — —

09h — Unimplemented — —

0Ah

(1,2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh

(1)

INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000u

0Ch PIR1 —ADIF— — — — — — -0-- ---- -0-- ----

0Dh — Unimplemented — —

0Eh — Unimplemented — —

0Fh — Unimplemented — —

10h — Unimplemented — —

11h — Unimplemented — —

12h — Unimplemented — —

13h — Unimplemented — —

14h — Unimplemented — —

15h — Unimplemented — —

16h — Unimplemented — —

17h — Unimplemented — —

18h — Unimplemented — —

19h — Unimplemented — —

1Ah — Unimplemented — —

1Bh — Unimplemented — —

1Ch — Unimplemented — —

1Dh — Unimplemented — —

1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0

reserved CHS1 CHS0 GO/DONE reserved ADON 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

3: Other (non power-up) resets include external reset through MCLR

and Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.

5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.