Datasheet

 1997-2013 Microchip Technology Inc. DS30561C-page 107
PIC12C67X
TABLE 12-9: EEPROM MEMORY BUS TIMING REQUIREMENTS - PIC12CE673/674 ONLY.
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0C  T
A  +70C, Vcc = 3.0V to 5.5V (commercial)
–40C  T
A  +85C, Vcc = 3.0V to 5.5V (industrial)
–40C  T
A  +125C, Vcc = 4.5V to 5.5V (extended)
Operating Voltage V
DD range is described in Section 12.1
Parameter Symbol Min Max Units Conditions
Clock frequency F
CLK —
—
—
100
100
400
kHz 4.5V Vcc  5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc  5.5V
Clock high time T
HIGH 4000
4000
600
—
—
—
ns 4.5V Vcc  5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc  5.5V
Clock low time T
LOW 4700
4700
1300
—
—
—
ns 4.5V Vcc  5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc  5.5V
SDA and SCL rise time
(Note 1)
T
R —
—
—
1000
1000
300
ns 4.5V Vcc  5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc  5.5V
SDA and SCL fall time T
F — 300 ns (Note 1)
START condition hold time THD:STA 4000
4000
600
—
—
—
ns 4.5V Vcc  5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc  5.5V
START condition setup time TSU:STA 4700
4700
600
—
—
—
ns 4.5V Vcc  5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc  5.5V
Data input hold time THD:DAT 0 — ns (Note 2)
Data input setup time TSU:DAT 250
250
100
—
—
—
ns 4.5V Vcc  5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc  5.5V
STOP condition setup time TSU:STO 4000
4000
600
—
—
—
ns 4.5V Vcc  5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc  5.5V
Output valid from clock
(Note 2)
TAA —
—
—
3500
3500
900
ns 4.5V Vcc  5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc  5.5V
Bus free time: Time the bus must
be free before a new transmis-
sion can start
TBUF 4700
4700
1300
—
—
—
ns 4.5V Vcc  5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc  5.5V
Output fall time from VIH
minimum to VIL maximum
T
OF 20+0.1
CB
250 ns (Note 1), CB 100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP — 50 ns (Notes 1, 3)
Write cycle time T
WC —4ms
Endurance 1M — cycles 25C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL and avoid unintended generation of START or STOP conditions.
3: The combined T
SP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific applica-
tion, please consult the Total Endurance Model which can be obtained on Microchip’s website.