Datasheet
1997-2013 Microchip Technology Inc. DS30561C-page 59
PIC12C67X
TABLE 9-6: RESET CONDITION FOR SPECIAL REGISTERS
TABLE 9-7: INITIALIZATION CON\DITIONS FOR ALL REGISTERS
Condition
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset 000h 0001 1xxx ---- --0-
MCLR
Reset during normal operation 000h 000u uuuu ---- --u-
MCLR
Reset during SLEEP 000h 0001 0uuu ---- --u-
WDT Reset during normal operation 000h 0000 uuuu ---- --u-
WDT Wake-up from SLEEP PC + 1 uuu0 0uuu ---- --u-
Interrupt wake-up from SLEEP PC + 1
(1)
uuu1 0uuu ---- --u-
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
Register Power-on Reset MCLR Resets
WDT Reset
Wake-up via
WDT or Interrupt
W xxxx xxxx uuuu uuuu uuuu uuuu
INDF 0000 0000 0000 0000 0000 0000
TMR0 xxxx xxxx uuuu uuuu uuuu uuuu
PCL 0000 0000 0000 0000 PC + 1
(2)
STATUS 0001 1xxx 000q quuu
(3)
uuuq quuu
(3)
FSR xxxx xxxx uuuu uuuu uuuu uuuu
GPIO
PIC12CE67X
11xx xxxx 11uu uuuu 11uu uuuu
GPIO
PIC12C67X
--xx xxxx --uu uuuu --uu uuuu
PCLATH ---0 0000 ---0 0000 ---u uuuu
INTCON 0000 000x 0000 000u uuuu uqqq
(1)
PIR1 -0-- ---- -0-- ---- -q-- ----
(4)
ADCON0 0000 0000 0000 0000 uuuu uquu
(5)
OPTION 1111 1111 1111 1111 uuuu uuuu
TRIS --11 1111 --11 1111 --uu uuuu
PIE1 -0-- ---- -0-- ---- -u-- ----
PCON ---- --0- ---- --u- ---- --u-
OSCCAL 0111 00-- uuuu uu-- uuuu uu--
ADCON1 ---- -000 ---- -000 ---- -uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.
Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 9-5 for reset value for specific condition.
4: If wake-up was due to A/D completing then bit 6 = 1, all other interrupts generating a wake-up will cause bit 6 = u.
5: If wake-up was due to A/D completing then bit 3 = 0, all other interrupts generating a wake-up will cause bit 3 = u.