PIC12C67X 8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory Devices Included in this Data Sheet: PDIP, SOIC, Windowed CERDIP PIC12C671 PIC12C672 PIC12CE673 PIC12CE674 Note: VDD GP5/OSC1/CLKIN GP4/OSC2/AN3/ CLKOUT GP3/MCLR/VPP Throughout this data sheet PIC12C67X refers to the PIC12C671, PIC12C672, PIC12CE673 and PIC12CE674. PIC12CE67X refers to PIC12CE673 and PIC12CE674.
PIC12C67X Table of Contents 1.0 General Description ...................................................................................................................................................................... 3 2.0 PIC12C67X Device Varieties ........................................................................................................................................................ 5 3.0 Architectural Overview ..............................................................................
PIC12C67X 1.0 GENERAL DESCRIPTION The PIC12C67X devices are low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with integrated analog-to-digital (A/D) converter and EEPROM data memory (EEPROM on PIC12CE67X versions only). All PIC® microcontrollers employ an advanced RISC architecture. The PIC12C67X microcontrollers have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources.
PIC12C67X TABLE 1-1: PIC12C67X & PIC12CE67X FAMILY OF DEVICES PIC12C671 Clock Memory Peripherals Features PIC12LC671 PIC12C672 PIC12LC672 PIC12CE673 PIC12LCE673 PIC12CE674 PIC12LCE674 Maximum Frequency of Operation (MHz) 10 10 10 10 10 10 10 10 EPROM Program Memory 1024 x 14 1024 x 14 2048 x 14 2048 x 14 1024 x 14 1024 x 14 2048 x 14 2048 x 14 RAM Data Memory (bytes) 128 128 128 128 128 128 128 128 EEPROM — Data Memory (bytes) — — — 16 16 16 16 Timer Module(s) TM
PIC12C67X 2.0 PIC12C67X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC12C67X Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For example, the PIC12C67X device “type” is indicated in the device number: 1. C, as in PIC12C671.
PIC12C67X NOTES: DS30561C-page 6 1997-2013 Microchip Technology Inc.
PIC12C67X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC12C67X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12C67X uses a Harvard architecture, in which program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus.
PIC12C67X FIGURE 3-1: PIC12C67X BLOCK DIAGRAM Program Memory Data Memory (RAM) Non-Volatile Memory (EEPROM) PIC12C671 1K x 14 128 x 8 — PIC12C672 2K x 14 128 x 8 — PIC12CE673 1K x 14 128 x 8 16 x 8 PIC12CE674 2K x 14 128 x 8 16 x 8 13 Program Bus GP0/AN0 GP1/AN1/VREF GP2/T0CKI/AN2/INT GP3/MCLR/VPP GP4/OSC2/AN3/CLKOUT GP5/OSC1/CLKIN RAM 128 bytes File Registers 8 Level Stack (13 bit) 14 RAM Addr (1) 9 Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr FSR reg 3 Power-u
PIC12C67X TABLE 3-1: PIC12C67X PINOUT DESCRIPTION DIP Pin # I/O/P Type GP0/AN0 7 I/O TTL/ST Bi-directional I/O port/serial programming data/analog input 0. Can be software programmed for internal weak pull-up and interrupt-on-pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. GP1/AN1/VREF 6 I/O TTL/ST Bi-directional I/O port/serial programming clock/analog input 1/ voltage reference.
PIC12C67X 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, and the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2.
PIC12C67X 4.0 MEMORY ORGANIZATION 4.1 Program Memory Organization The PIC12C67X has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC12C671 and the PIC12CE673, the first 1K x 14 (0000h-03FFh) is implemented. For the PIC12C672 and the PIC12CE674, the first 2K x 14 (0000h-07FFh) is implemented. Accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.
PIC12C67X FIGURE 4-2: PIC12C67X REGISTER FILE MAP File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address INDF(1) TMR0 PCL STATUS FSR GPIO INDF(1) OPTION PCL STATUS FSR TRIS PCLATH INTCON PIR1 PCLATH INTCON PIE1 PCON OSCCAL ADRES ADCON0 ADCON1 General Purpose Register General Purpose Register 70h 7Fh Mapped in Bank 0 Bank 0 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 9
PIC12C67X TABLE 4-1: Address PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other Resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(1) STATUS 04h(1) FSR 05h GPIO
PIC12C67X TABLE 4-1: Address PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.
PIC12C67X 4.2.2.1 STATUS REGISTER It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS Register, because these instructions do not affect the Z, C or DC bits from the STATUS Register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." The STATUS Register, shown in Register 4-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.
PIC12C67X 4.2.2.2 OPTION REGISTER Note: The OPTION Register is a readable and writable register, which contains various control bits to configure the TMR0/WDT prescaler, the External INT Interrupt, TMR0 and the weak pull-ups on GPIO. REGISTER 4-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer by setting bit PSA (OPTION<3>).
PIC12C67X 4.2.2.3 INTCON REGISTER Note: The INTCON Register is a readable and writable register, which contains various enable and flag bits for the TMR0 Register overflow, GPIO port change and external GP2/INT pin interrupts. REGISTER 4-3: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PIC12C67X 4.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the Peripheral interrupts. REGISTER 4-4: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC12C67X 4.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the Peripheral interrupts. REGISTER 4-5: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC12C67X 4.2.2.6 PCON REGISTER The Power Control (PCON) Register contains a flag bit to allow differentiation between a Power-on Reset (POR), an external MCLR Reset and a WDT Reset.
PIC12C67X 4.2.2.7 OSCCAL REGISTER The Oscillator Calibration (OSCCAL) Register is used to calibrate the internal 4 MHz oscillator. It contains four bits for fine calibration and two other bits to either increase or decrease frequency.
PIC12C67X 4.3 PCL and PCLATH 4.3.2 The Program Counter (PC) is 13-bits wide. The low byte comes from the PCL Register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-3 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
PIC12C67X 4.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 4-1: The INDF Register is not a physical register. Addressing the INDF Register will cause indirect addressing. movlw movwf clrf incf btfss goto NEXT Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF Register itself indirectly (FSR = '0') will read 00h.
PIC12C67X NOTES: DS30561C-page 24 1997-2013 Microchip Technology Inc.
PIC12C67X 5.0 I/O PORT As with any other register, the I/O register can be written and read under program control. However, read instructions (i.e., MOVF GPIO,W) always read the I/O pins independent of the pin’s input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance), since the I/O control registers are all set. 5.1 GPIO GPIO is an 8-bit I/O register. Only the low order 6 bits are used (GP<5:0>).
PIC12C67X FIGURE 5-1: BLOCK DIAGRAM OF GP0/AN0 AND GP1/AN1/VREF PIN GPPU Data Bus WR PORT D Q CK Q VDD VDD P P VDD I/O Pin Data Latch N WR TRIS D Q CK Q VSS VSS TRIS Latch Analog Input Mode TTL Input Buffer RD TRIS Q D EN RD PORT GP0/INT(1) and GP1/INT(1) To A/D Converter Note 1: Wake-up on pin change interrupts for GP0 and GP1. DS30561C-page 26 1997-2013 Microchip Technology Inc.
PIC12C67X FIGURE 5-2: BLOCK DIAGRAM OF GP2/T0CKI/AN2/INT PIN Data Bus WR PORT D Q CK Q VDD VDD P I/O Pin Data Latch N WR TRIS D Q CK Q VSS VSS TRIS Latch Analog Input Mode Schmitt Trigger Input Buffer RD TRIS Q D EN RD PORT TMR0 Clock Input GP2/INT To A/D Converter 1997-2013 Microchip Technology Inc.
PIC12C67X FIGURE 5-3: BLOCK DIAGRAM OF GP3/MCLR/VPP PIN VDD GPPU P MCLREN Input Pin VSS MCLR Schmitt Trigger Input Buffer Program Mode HV Detect TTL Input Buffer Data Bus Q D EN RD PORT RD TRIS VSS GP3/INT(1) Note 1: Wake-up on pin change interrupt for GP3. DS30561C-page 28 1997-2013 Microchip Technology Inc.
PIC12C67X FIGURE 5-4: BLOCK DIAGRAM OF GP4/OSC2/AN3/CLKOUT PIN INTRC or EXTRC w/ CLKOUT CLKOUT (FOSC/4) 1 0 From OSC1 Data Bus D WR PORT CK Q VDD Q Oscillator Circuit VDD P I/O Pin Data Latch N VSS WR TRIS D Q CK Q INTRC/ EXTRC VSS INTRC or EXTRC w/o CLKOUT TRIS Latch Analog Input Mode TTL Input Buffer RD TRIS Q D EN RD PORT To A/D Converter 1997-2013 Microchip Technology Inc.
PIC12C67X FIGURE 5-5: BLOCK DIAGRAM OF GP5/OSC1/CLKIN PIN To OSC2 Oscillator Circuit Data Bus WR PORT D Q EN Q VDD VDD P Data Latch I/O Pin N WR TRIS D Q EN Q INTRC VSS VSS TRIS Latch INTRC TTL Input Buffer RD TRIS Q D EN RD PORT DS30561C-page 30 1997-2013 Microchip Technology Inc.
PIC12C67X TABLE 5-1: Address 85h SUMMARY OF PORT REGISTERS Name TRIS Bit 7 Bit 6 — — INTEDG 81h OPTION GPPU 03h STATUS IRP (1) 05h GPIO SCL(2) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GPIO Data Direction Register Value on Power-on Reset Value on all other Resets --11 1111 --11 1111 T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 (1) RP0 TO PD Z DC C 0001 1xxx 000q quuu SDA(2) GP5 GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu RP1 Legend: Shaded cells not used by Por
PIC12C67X NOTES: DS30561C-page 32 1997-2013 Microchip Technology Inc.
PIC12C67X 6.0 EEPROM PERIPHERAL OPERATION The PIC12CE673 and PIC12CE674 each have 16 bytes of EEPROM data memory. The EEPROM memory has an endurance of 1,000,000 erase/write cycles and a data retention of greater than 40 years. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol. These two-wires are serial data (SDA) and serial clock (SCL), that are mapped to bit6 and bit7, respectively, of the GPIO register (SFR 06h).
PIC12C67X 6.1.5 ACKNOWLEDGE The EEPROM, when addressed, will generate an acknowledge after the reception of each byte. The processor must generate an extra clock pulse which is associated with this acknowledge bit. Note: Acknowledge bits are not generated if an internal programming cycle is in progress.
PIC12C67X FIGURE 6-3: SCL (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (C) (D) START CONDITION ADDRESS OR ACKNOWLEDGE VALID (C) (A) SDA FIGURE 6-4: STOP CONDITION DATA ALLOWED TO CHANGE ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 SDA 3 4 5 6 7 8 9 1 Device Addressing After generating a START condition, the processor transmits a control byte consisting of a EEPROM address and a Read/Write bit that indicates what type of operation is to be performed.
PIC12C67X 6.3 Write Operations 6.4 6.3.1 BYTE WRITE Since the EEPROM will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the processor, the device initiates the internally timed write cycle. ACK polling can be initiated immediately.
PIC12C67X 6.5 Read Operations address is sent, the processor generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the processor issues the control byte again, but with the R/W bit set to a one. The EEPROM will then issue an acknowledge and transmits the 8-bit data word. The processor will not acknowledge the transfer, but does generate a stop condition and the EEPROM discontinues transmission (Figure 6-9).
PIC12C67X NOTES: DS30561C-page 38 1997-2013 Microchip Technology Inc.
PIC12C67X 7.0 TIMER0 MODULE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. The Timer0 module timer/counter has the following features: • • • • • • The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module.
PIC12C67X FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 MOVWF TMR0 MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W Instruction Fetch T0 TMR0 T0+1 Instruction Execute Write TMR0 executed FIGURE 7-4: NT0+1 NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 TI
PIC12C67X 7.2 Using Timer0 with an External Clock caler, so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns.
PIC12C67X 7.3 The PSA and PS<2:0> bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. Prescaler An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 7-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer.
PIC12C67X 7.3.1 SWITCHING PRESCALER ASSIGNMENT To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 7-2. The prescaler assignment is fully under software control, (i.e., it can be changed “on-the-fly” during program execution). Note: To avoid an unintended device RESET, the following instruction sequence (shown in Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
PIC12C67X NOTES: DS30561C-page 44 1997-2013 Microchip Technology Inc.
PIC12C67X 8.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-To-Digital (A/D) converter module has four analog inputs. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation.
PIC12C67X REGISTER 8-2: U-0 — bit7 ADCON1 REGISTER (ADDRESS 9Fh) U-0 — U-0 — U-0 — U-0 — R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1-0: PCFG<2:0>: A/D Port Configuration Control bits PCFG<2:0> GP4 GP2 GP1 GP0 VREF 000(1) 001 010 011 100 101 110 111 A A A A VDD A D D D D D D A A A D D D D VREF A VREF A VREF D D A A A A A A D GP1 VDD GP1 VDD GP1 VDD VDD
PIC12C67X The ADRES Register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF (PIE1<6>) is set. The block diagrams of the A/D module are shown in Figure 8-1. 2. 3. 4. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started.
PIC12C67X 8.1 A/D Sampling Requirements Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 8-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD.
PIC12C67X 8.2 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5 TAD per 8-bit conversion. The source of the A/D conversion clock is software selected. The four possible options for TAD are: • • • • 2TOSC 8TOSC 32TOSC Internal ADC RC oscillator Configuring Analog Port Pins The ADCON1 and TRIS Registers control the operation of the A/D port pins.
PIC12C67X 8.4 A/D Conversions Example 8-2 shows how to perform an A/D conversion. The GPIO pins are configured as analog inputs. The analog reference (VREF) is the device VDD. The A/D interrupt is enabled and the A/D conversion clock is FRC. The conversion is performed on the GP0 channel. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
PIC12C67X A/D Accuracy/Error The overall accuracy of the A/D is less than 1 LSb for VDD = 5V 10% and the analog VREF = VDD. This overall accuracy includes offset error, full scale error, and integral error. The A/D converter is monotonic over the full VDD range. The resolution and accuracy may be less when either the analog reference (VDD) is less than 5.0V or when the analog reference (VREF) is less than VDD.
PIC12C67X FIGURE 8-4: FLOWCHART OF A/D OPERATION ADON = 0 Yes ADON = 0? No Acquire Selected Channel Yes GO = 0? No Yes A/D Clock = RC? Start of A/D Conversion Delayed 1 Instruction Cycle SLEEP Yes Instruction? Finish Conversion GO = 0 ADIF = 1 No No Yes Device in SLEEP? Abort Conversion GO = 0 ADIF = 0 Wake-up Yes From Sleep? Finish Conversion GO = 0 ADIF = 1 Wait 2 TAD No No SLEEP Power-down A/D Finish Conversion GO = 0 ADIF = 1 Stay in Sleep Power-down A/D Wait 2 TAD Wait 2 TAD T
PIC12C67X 9.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC12C67X family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC12C67X 9.2 Oscillator Configurations 9.2.1 OSCILLATOR TYPES TABLE 9-1: The PIC12C67X can be operated in seven different oscillator modes. The user can program three configuration bits (FOSC<2:0>) to select one of these seven modes: • • • • • LP: HS: XT: INTRC*: EXTRC*: Low Power Crystal High Speed Crystal/Resonator Crystal/Resonator Internal 4 MHz Oscillator External Resistor/Capacitor *Can be configured to support CLKOUT 9.2.
PIC12C67X 9.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a pre-packaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Pre-packaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with parallel resonance or one with series resonance.
PIC12C67X 9.2.5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25°C. See Section 13.0 for information on variation over voltage and temperature. In addition, a calibration instruction is programmed into the last address of the program memory which contains the calibration value for the internal RC oscillator. This value is programmed as a RETLW XX instruction where XX is the calibration value.
PIC12C67X FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Weak Pull-up GP3/MCLR/VPP Pin MCLRE INTERNAL MCLR WDT SLEEP Module WDT Time-out VDD rise detect Power-on Reset VDD S OST/PWRT OST Chip_Reset 10-bit Ripple-counter OSC1/ CLKIN Pin On-chip(1) RC OSC R Q PWRT 10-bit Ripple-counter Enable PWRT See Table 9-4 for time-out situations. Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 1997-2013 Microchip Technology Inc.
PIC12C67X 9.4 Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) 9.4.1 POWER-ON RESET (POR) The on-chip POR circuit holds the chip in reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, just tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create a Poweron Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details.
PIC12C67X TABLE 9-6: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 000h 0001 1xxx ---- --0- MCLR Reset during normal operation 000h 000u uuuu ---- --u- MCLR Reset during SLEEP 000h 0001 0uuu ---- --u- WDT Reset during normal operation 000h 0000 uuuu ---- --u- PC + 1 uuu0 0uuu ---- --u- PC + 1(1) uuu1 0uuu ---- --u- Condition WDT Wake-up from SLEEP Interrupt wake-up from SLEEP Legend: u = unchanged, x = unknown, - = unimplemente
PIC12C67X FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 9-8: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30561C-page 60 1997-2013 Microchip Technology I
PIC12C67X FIGURE 9-10: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 9-11: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD D VDD 33k VDD 10k R R1 4.3k MCLR C MCLR PIC12C67X PIC12C67X Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device’s electrical specification.
PIC12C67X 9.5 Interrupts The “return-from-interrupt” instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts. There are four sources of interrupt: Interrupt Sources TMR0 Overflow Interrupt External Interrupt GP2/INT pin GPIO Port Change Interrupts (pins GP0, GP1, GP3) A/D Interrupt The Interrupt Control Register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits.
PIC12C67X FIGURE 9-14: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 4 INT pin INTF flag (INTCON<1>) 1 1 Interrupt Latency 2 5 GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction fetched Inst (PC) Instruction executed Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) 0004h PC+1 — Dummy Cycle 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) Note 1: INTF flag is sampled here (every Q1).
PIC12C67X 9.5.1 9.6 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>) (Section 7.0). The flag bit T0IF (INTCON<2>) will be set, regardless of the state of the enable bits. If used, this flag must be cleared in software. 9.5.
PIC12C67X 9.7 Watchdog Timer (WDT) The Watchdog Timer is a free running, on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset).
PIC12C67X 9.8 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low or hi-impedance).
PIC12C67X FIGURE 9-16: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) GPIO pin GPIF flag (INTCON<0>) Interrupt Latency (Note 3) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = SLEEP Instruction executed Inst(PC - 1) PC+1 PC+2 PC+2 PC + 2 Inst(PC + 1) Inst(PC + 2) SLEEP Inst(PC + 1) Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Ins
PIC12C67X NOTES: DS30561C-page 68 1997-2013 Microchip Technology Inc.
PIC12C67X 10.0 INSTRUCTION SET SUMMARY Each PIC12C67X instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC12C67X instruction set summary in Table 10-2 lists byte-oriented, bitoriented, and literal and control operations. Table 101 shows the opcode field descriptions.
PIC12C67X 10.1 Special Function Registers as Source/Destination The PIC12C67X’s orthogonal instruction set allows read and write of all file registers, including special function registers. There are some special situations the user should be aware of: 10.1.1 STATUS AS DESTINATION If an instruction writes to STATUS, the Z, C and DC bits may be set or cleared as a result of the instruction and overwrite the original data bits written.
PIC12C67X TABLE 10-2: Mnemonic, Operands INSTRUCTION SET SUMMARY Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f
PIC12C67X 10.2 Instruction Descriptions ADDLW Add Literal and W ANDLW And Literal with W Syntax: [ label ] ANDLW Syntax: [ label ] ADDLW Operands: 0 k 255 Operands: 0 k 255 Operation: (W) + k (W) Operation: (W) .AND. (k) (W) Status Affected: C, DC, Z Status Affected: Z Encoding: 11 k 111x kkkk kkkk Encoding: 11 k 1001 kkkk kkkk Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
PIC12C67X BCF Bit Clear f BTFSC Bit Test, Skip if Clear Syntax: [ label ] BCF Syntax: [ label ] BTFSC f,b Operands: 0 f 127 0b7 Operands: 0 f 127 0b7 Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 01 f,b 00bb bfff ffff Description: Bit 'b' in register 'f' is cleared.
PIC12C67X BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRF Operands: 0 f 127 0b<7 Operands: 0 f 127 Operation: Operation: skip if (f) = 1 00h (f) 1Z Status Affected: None Status Affected: Z Encoding: Description: 01 11bb bfff ffff If bit 'b' in register 'f' is '1', then the next instruction is skipped.
PIC12C67X CLRWDT Clear Watchdog Timer DECF Decrement f Syntax: [ label ] CLRWDT Syntax: [ label ] DECF f,d Operands: None Operands: Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD 0 f 127 d [0,1] Operation: (f) - 1 (dest) Status Affected: Z TO, PD Encoding: Status Affected: Encoding: Description: 00 0000 0110 0100 Description: 00 Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example CNT Z WDT counter = ? WDT counter = WDT prescaler= TO = PD = COMF Complement f
PIC12C67X GOTO Unconditional Branch INCFSZ Increment f, Skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 k 2047 Operands: Operation: k PC<10:0> PCLATH<4:3> PC<12:11> 0 f 127 d [0,1] Operation: (f) + 1 (dest), skip if result = 0 None Status Affected: None Status Affected: Encoding: GOTO k 10 1kkk kkkk kkkk Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>.
PIC12C67X IORWF Inclusive OR W with f MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (W) .OR. (f) (dest) Operation: (f) (dest) Status Affected: Z Status Affected: Z Encoding: 00 IORWF f,d 0100 dfff ffff Description: Inclusive OR the W register with register 'f'. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
PIC12C67X NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS PC, 1 GIE Status Affected: None Encoding: 00 NOP 0000 Description: No operation. Words: 1 Cycles: 1 Example 0xx0 0000 Encoding: 00 RETFIE 0000 0000 1001 Description: Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC.
PIC12C67X RETURN Return from Subroutine RRF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: TOS PC 0 f 127 d [0,1] Status Affected: None Operation: See description below Status Affected: C Encoding: Description: 00 0000 0000 1000 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.
PIC12C67X SUBLW Syntax: Subtract W from Literal [ label ] SUBLW k SUBWF Syntax: Subtract W from f [ label ] SUBWF f,d Operands: 0 k 255 Operands: Operation: k - (W) W) 0 f 127 d [0,1] Status Affected: C, DC, Z Operation: (f) - (W) dest) Status Affected: C, DC, Z Encoding: 00 Encoding: Description: 11 110x kkkk kkkk The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.
PIC12C67X SWAPF Swap Nibbles in f XORLW Exclusive OR Literal with W Syntax: [ label ] SWAPF f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) Operation: (W) .XOR. k W) Status Affected: Z None Encoding: Operation: Status Affected: Encoding: Description: 00 1110 dfff ffff The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in W register.
PIC12C67X NOTES: DS30561C-page 82 1997-2013 Microchip Technology Inc.
PIC12C67X 11.
PIC12C67X MPLIB is a librarian for pre-compiled code to be used with MPLINK. When a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. MPLIB manages the creation and modification of library files. MPLINK features include: • MPLINK works with MPASM and MPLAB-C17 and MPLAB-C18.
PIC12C67X stand-alone mode the PRO MATE II can read, verify or program PIC devices. It can also set code-protect bits in this mode. 11.11 PICSTART Plus Entry Level Development System The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus supports all PIC devices with up to 40 pins.
PIC12C67X and test the sample code. In addition, PICDEM-17 supports down-loading of programs to and executing out of external FLASH memory on board. The PICDEM-17 is also usable with the MPLAB-ICE or PICMASTER emulator, and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware. 11.17 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs.
1997-2013 Microchip Technology Inc.
PIC12C67X NOTES: DS30561C-page 10-88 1997-2013 Microchip Technology Inc.
PIC12C67X 12.0 ELECTRICAL SPECIFICATIONS FOR PIC12C67X Absolute Maximum Ratings † Ambient temperature under bias...............................................................................................................–40° to +125°C Storage temperature ............................................................................................................................. –65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR)..................................................
PIC12C67X FIGURE 12-1: PIC12C67X VOLTAGE-FREQUENCY GRAPH, -40C TA 0C, +70C TA +125C 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 20 10 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
PIC12C67X FIGURE 12-3: PIC12LC67X VOLTAGE-FREQUENCY GRAPH, -40C TA +85C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. 1997-2013 Microchip Technology Inc.
PIC12C67X 12.1 DC Characteristics: PIC12C671/672 (Commercial, Industrial, Extended) PIC12CE673/674 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C TA +70°C (commercial) –40°C TA +85°C (industrial) –40°C TA +125°C (extended) DC CHARACTERISTICS Parm No.
PIC12C67X Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C TA +70°C (commercial) –40°C TA +85°C (industrial) –40°C TA +125°C (extended) DC CHARACTERISTICS Parm No.
PIC12C67X 12.2 DC Characteristics: PIC12LC671/672 (Commercial, Industrial) PIC12LCE673/674 (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) Operating temperature 0°C TA +70°C (commercial) –40°C TA +85°C (industrial) DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units 2.5 5.5 Conditions V D001 Supply Voltage VDD D002 RAM Data Retention Voltage(2) VDR 1.
PIC12C67X 12.3 DC CHARACTERISTICS: DC CHARACTERISTICS Param No.
PIC12C67X DC CHARACTERISTICS Param No. Characteristic Output High Voltage I/O ports (Note 3) D090 Standard Operating Conditions (unless otherwise specified) Operating temperature 0°C TA +70°C (commercial) –40°C TA +85°C (industrial) –40°C TA +125°C (extended) Operating voltage VDD range as described in DC spec Section 12.1 and Section 12.2. Sym Min Typ† Max Units Conditions VDD - 0.7 — — V VDD - 0.7 — — V VDD - 0.7 — — V VDD - 0.
PIC12C67X 12.4 DC CHARACTERISTICS: DC CHARACTERISTICS Param No.
PIC12C67X DC CHARACTERISTICS Param No. Characteristic Output High Voltage I/O ports (Note 3) D090 Standard Operating Conditions (unless otherwise specified) Operating temperature 0°C TA +70°C (commercial) –40°C TA +85°C (industrial) Operating voltage VDD range as described in DC spec Section 12.1 and Section 12.2. Sym Min Typ† Max Units Conditions VOH VDD - 0.7 — — V VDD - 0.7 — — V VDD - 0.7 — — V VDD - 0.
PIC12C67X 12.5 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC12C67X 12.6 Timing Diagrams and Specifications FIGURE 12-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 12-1: Parameter No. CLOCK TIMING REQUIREMENTS Sym Characteristic Min Typ† Max Units Conditions DC — 4 MHz XT and EXTRC osc mode DC — 4 MHz HS osc mode (PIC12CE67X-04) DC — 10 MHz HS osc mode (PIC12CE67X-10) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz EXTRC osc mode (Note 1) .
PIC12C67X TABLE 12-2: CALIBRATED INTERNAL RC FREQUENCIES -PIC12C671, PIC12C672, PIC12CE673, PIC12CE674, PIC12LC671, PIC12LC672, PIC12LCE673, PIC12LCE674 AC Characteristics Parameter No. * Note 1: Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), –40C TA +85C (industrial), –40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1 Min* Typ(1) Internal Calibrated RC Frequency 3.65 4.00 4.28 MHz VDD = 5.
PIC12C67X FIGURE 12-6: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 12-4 for load conditions. TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym No.
PIC12C67X FIGURE 12-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Timeout 32 OSC Timeout Internal RESET Watchdog Timer RESET 36 34 31 34 I/O Pins TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER Parameter No.
PIC12C67X FIGURE 12-8: TIMER0 CLOCK TIMINGS GP2/T0CKI 41 40 42 TMR0 Note: Refer to Figure 12-4 for load conditions. TABLE 12-5: Param No. Sym 40* Tt0H TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Characteristic T0CKI High Pulse Width Min No Prescaler 0.5TCY + 20 — — ns 10 — — ns With Prescaler 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.
PIC12C67X TABLE 12-7: Param No. Sym A01 NR A02 A/D CONVERTER CHARACTERISTICS: PIC12C671/672-04/PIC12CE673/674-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC12C671/672-10/PIC12CE673/674-10 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC12LC671/672-04/PIC12LCE673/674-04 (COMMERCIAL, INDUSTRIAL) Characteristic Resolution EABS Total absolute error Min Typ† Max Units Conditions — — 8-bits bit VREF = VDD = 5.12V, VSS VAIN VREF — — < 1 LSb VREF = VDD = 5.
PIC12C67X FIGURE 12-9: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (TOSC/2)(1) 131 Q4 130 132 A/D CLK 7 A/D DATA 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 12-8: A/D CONVERSION REQUIREMENTS Param No. Sym Characteristic 130 TAD A/D clock period Min 1.6 — — s TOSC based, VREF 3.
PIC12C67X TABLE 12-9: EEPROM MEMORY BUS TIMING REQUIREMENTS - PIC12CE673/674 ONLY. AC Characteristics Parameter Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C, Vcc = 3.0V to 5.5V (commercial) –40C TA +85C, Vcc = 3.0V to 5.5V (industrial) –40C TA +125C, Vcc = 4.5V to 5.5V (extended) Operating Voltage VDD range is described in Section 12.1 Symbol Min Max Units Conditions Clock frequency FCLK — — — 100 100 400 kHz 4.5V Vcc 5.
PIC12C67X NOTES: DS30561C-page 108 1997-2013 Microchip Technology Inc.
PIC12C67X 13.0 DC AND AC CHARACTERISTICS - PIC12C671/PIC12C672/PIC12LC671/ PIC12LC672/PIC12CE673/PIC12CE674/PIC12LCE673/PIC12LCE674 The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices will operate properly only within the specified range.
PIC12C67X TABLE 13-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C Oscillator Frequency External RC 4 MHz Internal RC 4 MHz XT 4 MHz LP 32 kHz *Does not include current through external R&C. VDD = 2.5V VDD = 5.5V 400 µA* 400 µA 400 µA 15 µA 900 µA* 900 µA 900 µA 60 µA FIGURE 13-4: IOH vs. VOH, VDD = 2.5 V FIGURE 13-3: WDT TIMER TIME-OUT PERIOD vs.
PIC12C67X FIGURE 13-5: IOH vs. VOH, VDD = 3.5 V FIGURE 13-7: IOL vs. VOL, VDD = 2.5 V 35 0 30 -5 IOH (mA) Max -40C Min +125C 25 -10 IOL (mA) Min +85C Typ +25C -15 20 Typ +25C 15 Max -40C -20 Min +85C 10 Min +125C -25 1.5 2.0 2.5 3.0 3.5 5 VOH (Volts) 0 0 FIGURE 13-6: IOH vs. VOH, VDD = 5.5 V 0.25 0.5 0.75 1.0 VOL (Volts) 0 FIGURE 13-8: IOL vs. VOL, VDD = 3.
PIC12C67X FIGURE 13-9: IOL vs. VOL, VDD = 5.5 V FIGURE 13-10: VTH (INPUT THRESHOLD VOLTAGE) OF GPIO PINS vs. VDD 55 1.8 Max -40C 50 Max (-40 to 125) VTH (Volts) 1.6 45 40 1.4 Typ (25 1.2 35 IOL (mA) Typ +25C Min (-40 to 125) 1.0 30 0.8 25 Min +85C 20 15 Min +125C 0.6 0 2.5 3.5 4.5 VDD (Volts) 5.5 10 0 0 0.25 0.5 0.75 1.0 VOL (Volts) DS30561C-page 112 1997-2013 Microchip Technology Inc.
PIC12C67X FIGURE 13-11: VIL, VIH OF NMCLR AND T0CKI vs. VDD 3.5 VIH Max (-40 to 125) VIH Typ (25 VIH Min (-40 to 125) VIL, VIH (Volts) 3.0 2.5 2.0 VIL Max (-40 to 125) 1.5 VIL Typ (25 VIL Min (-40 to 125) 1.0 0.5 2.5 3.5 4.5 5.5 VDD (Volts) 1997-2013 Microchip Technology Inc.
PIC12C67X NOTES: DS30561C-page 114 1997-2013 Microchip Technology Inc.
PIC12C67X 14.0 PACKAGING INFORMATION 14.1 Package Marking Information 8-Lead PDIP (300 mil) MMMMMMMM XXXXXCDE AABB 12CE674 04/PSAZ 9925 8-Lead SOIC (208 mil) MMMMMMM XXXXXXX AABBCDE Example JW MM CE674 MMMMMM Legend: MM...M XX...
PIC12C67X 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c A1 B1 p eB B Units Dimension Limits n p MIN INCHES* NOM MAX MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins 8 Pitch .100 Top to Seating Plane A .140 .155 .
PIC12C67X 8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC12C67X 8-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC12C67X APPENDIX A: COMPATIBILITY To convert code written for PIC16C5X to PIC12C67X, the user should take the following steps: 1. 2. 3. 4. 5. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables to reallocate them.
PIC12C67X NOTES: DS30561C-page 120 1997-2013 Microchip Technology Inc.
PIC12C67X INDEX A A/D Accuracy/Error ............................................................ 51 ADCON0 Register....................................................... 45 ADIF bit ....................................................................... 47 Analog Input Model Block Diagram............................. 48 Analog-to-Digital Converter......................................... 45 Configuring Analog Port Pins...................................... 49 Configuring the Interrupt ....................
PIC12C67X I K I/O Interfacing...................................................................... 25 I/O Ports .............................................................................. 25 I/O Programming Considerations........................................ 31 ID Locations ........................................................................ 53 INCF Instruction .................................................................. 76 INCFSZ Instruction...............................................
PIC12C67X Power-down Mode (SLEEP) ............................................... 66 Prescaler, Switching Between Timer0 and WDT ................ 43 PRO MATE II Universal Programmer .............................. 85 Program Branches ................................................................ 7 Program Memory Paging......................................................................... 22 Program Verification ........................................................... 67 PS0 bit .....................
PIC12C67X NOTES: DS30561C-page 124 1997-2013 Microchip Technology Inc.
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PIC12C67X PIC12C67X PRODUCT IDENTIFICATION SYSTEM Examples PART NO.
PIC12C67X DS30561C-page 128 1997-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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