Datasheet

 1999 Microchip Technology Inc. DS40139E-page 89
PIC12C5XX
FIGURE 13-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING -
PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A,
PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519
TABLE 13-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12C508A,
PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A,
PIC12LCR509A, PIC12LCE518 and PIC12LCE519
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ T
A ≤ +70°C (commercial)
–40°C ≤ T
A ≤ +85°C (industrial)
–40°C ≤ T
A ≤ +125°C (extended)
Operating Voltage V
DD range is described in Section 13.1
Parameter
No. Sym Characteristic Min Typ
(1)
Max Units Conditions
30
TmcL MCLR Pulse Width (low) 2000* — — ns VDD = 5 V
31
Twdt Watchdog Timer Time-out Period
(No Prescaler)
9* 18* 30* ms VDD = 5 V (Commercial)
32
TDRT Device Reset Timer Period
(2)
9* 18* 30* ms VDD = 5 V (Commercial)
34
TioZ I/O Hi-impedance from MCLR Low — — 2000* ns
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 2: See Table 13-6.
VDD
MCLR
Internal
POR
DRT
Timeout
Internal
RESET
Watchdog
Timer
RESET
32
31
34
I/O pin
32
32
34
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
30
(Note 2)
2: Runs in MCLR or WDT reset only in XT and LP modes.