Datasheet

PIC12C5XX
DS40139E-page 10  1999 Microchip Technology Inc.
FIGURE 3-1: PIC12C5XX BLOCK DIAGRAM
Device Reset
Timer
Power-on
Reset
Watchdog
Timer
ROM/EPROM
Program
Memory
12
Data Bus
8
12
Program
Bus
Instruction reg
Program Counter
RAM
File
Registers
Direct Addr
5
RAM Addr
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2
MCLR
VDD, VSS
Timer0
GPIO
8
8
GP4/OSC2
GP3/MCLR/VPP
GP2/T0CKI
GP1
GP0
5-7
3
GP5/OSC1/CLKIN
STACK1
STACK2
512 x 12 or
25 x 8 or
1024 x 12
4
1
x
8
Internal RC
OSC
16 X 8
EEPROM
Data
Memory
PIC12CE5XX
Only
SDA
SCL