Datasheet

PIC12C5XX
DS40139E-page 32  1999 Microchip Technology Inc.
FIGURE 7-3: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 7-4: ACKNOWLEDGE TIMING
(A)
(B)
(C)
(D)
(A)(C)
SCL
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SCL
987654321123
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
Data from transmitter
SDA
Acknowledge
Bit
7.2 Device Addressing
After generating a START condition, the bus master
transmits a control byte consisting of a slave address
and a Read/Write
bit that indicates what type of opera-
tion is to be performed. The slave address consists of
a 4-bit device code (1010) followed by three don’t care
bits.
The last bit of the control byte determines the operation
to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. (Figure 7-5). The bus is monitored for its cor-
responding slave address all the time. It generates an
acknowledge bit if the slave address was true and it is
not in a programming mode.
FIGURE 7-5: CONTROL BYTE FORMAT
1010XXXSACKR/W
Device Select
Bits
Don’t Care
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write
Bit