Datasheet

 1999 Microchip Technology Inc. DS40139E-page 39
PIC12C5XX
TABLE 8-3: RESET CONDITIONS FOR REGISTERS
TABLE 8-4: RESET CONDITION FOR SPECIAL REGISTERS
Register Address Power-on Reset
MCLR
Reset
WDT time-out
Wake-up on Pin Change
W (PIC12C508/509)
—
qqqq xxxx
(1)
qqqq uuuu
(1)
W (PIC12C508A/509A/
PIC12CE518/519/
PIC12CE509A)
—
qqqq qqxx
(1)
qqqq qquu
(1)
INDF 00h xxxx xxxx uuuu uuuu
TMR0 01h xxxx xxxx uuuu uuuu
PC 02h 1111 1111 1111 1111
STATUS 03h 0001 1xxx
q00q quuu
(2,3)
FSR (PIC12C508/
PIC12C508A/
PIC12CE518)
04h 111x xxxx 111u uuuu
FSR (PIC12C509/
PIC12C509A/
PIC12CE519/
PIC12CR509A)
04h 110x xxxx 11uu uuuu
OSCCAL
(PIC12C508/509)
05h 0111 ---- uuuu ----
OSCCAL
(PIC12C508A/509A/
PIC12CE518/512/
PIC12CR509A)
05h 1000 00-- uuuu uu--
GPIO
(PIC12C508/PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)
06h --xx xxxx --uu uuuu
GPIO
(PIC12CE518/
PIC12CE519)
06h
11xx xxxx 11uu uuuu
OPTION — 1111 1111 1111 1111
TRIS — --11 1111 --11 1111
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory.
Note 2: See Table 8-7 for reset value for specific conditions
Note 3: If reset was due to wake-up on pin change, then bit 7 = 1. All other resets will cause bit 7 = 0.
STATUS Addr: 03h PCL Addr: 02h
Power on reset 0001 1xxx 1111 1111
MCLR
reset during normal operation 000u uuuu 1111 1111
MCLR
reset during SLEEP 0001 0uuu 1111 1111
WDT reset during SLEEP 0000 0uuu 1111 1111
WDT reset normal operation 0000 uuuu 1111 1111
Wake-up from SLEEP on pin change 1001 0uuu 1111 1111
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’.