Datasheet

PIC12C5XX
DS40139E-page 42  1999 Microchip Technology Inc.
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
VDD
MCLR
INTERNAL POR
DRT TIME-OUT
INTERNAL RESET
TDRT
V1
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
8.5 Device Reset Timer (DRT)
In the PIC12C5XX, DRT runs from RESET and varies
based on oscillator selection (see Table 8-5.)
The DRT operates on an internal RC oscillator. The
processor is kept in RESET as long as the DRT is
active. The DRT delay allows V
DD to rise above VDD
min., and for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after MCLR
has reached a logic high (VIHMCLR)
level. Thus, programming GP3/MCLR
/VPP as MCLR
and using an external RC network connected to the
MCLR
input is not required in most cases, allowing for
savings in cost-sensitive and/or space restricted
applications, as well as allowing the use of the GP3/
MCLR
/VPP pin as a general purpose input.
The Device Reset time delay will vary from chip to chip
due to V
DD, temperature, and process variation. See
AC parameters for details.
The DRT will also be triggered upon a Watchdog
Timer time-out. This is particularly important for
applications using the WDT to wake from SLEEP
mode automatically.
8.6 Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the GP5/OSC1/CLKIN pin
and the internal 4 MHz oscillator. That means that the
WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or SLEEP, a WDT
reset or wake-up reset generates a device RESET.
The TO
bit (STATUS<4>) will be cleared upon a
Watchdog Timer reset.
The WDT can be permanently disabled by
programming the configuration bit WDTE as a ’0’
(Section 8.1). Refer to the PIC12C5XX Programming
Specifications to determine how to access the
configuration word.
TABLE 8-5: DRT (DEVICE RESET TIMER
PERIOD)
Oscillator
Configuration
POR Reset
Subsequent
Resets
IntRC &
ExtRC
18 ms (typical) 300 µs (typical)
XT & LP 18 ms (typical) 18 ms (typical)