PIC12C5XX 8-Pin, 8-Bit CMOS Microcontrollers Devices included in this Data Sheet: Peripheral Features: • PIC12C508 • PIC12C508A • PIC12C509 • PIC12C509A • PIC12CR509A • PIC12CE518 • PIC12CE519 PIC12C508 512 x 12 25 • 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler • Power-On Reset (POR) • Device Reset Timer (DRT) • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Programmable code-protection • 1,000,000 erase/write cycle EEPROM data memory • EEPR
PIC12C5XX Pin Diagram - PIC12C508/509 PDIP, 208 mil SOIC, Windowed Ceramic Side Brazed 1 2 GP4/OSC2 GP3/MCLR/VPP 3 PIC12C508 PIC12C509 VDD GP5/OSC1/CLKIN 4 8 VSS 7 GP0 6 GP1 5 GP2/T0CKI Pin Diagram - PIC12C508A/509A, PIC12CE518/519 PDIP, 150 & 208 mil SOIC, Windowed CERDIP 1 2 GP4/OSC2 GP3/MCLR/VPP 3 4 PIC12C508A PIC12C509A PIC12CE518 PIC12CE519 VDD GP5/OSC1/CLKIN 8 VSS 7 GP0 6 GP1 5 GP2/T0CKI 8 VSS 7 GP0 6 GP1 5 GP2/T0CKI Pin Diagram - PIC12CR509A PDIP, 150 & 208 mil SOIC
PIC12C5XX TABLE OF CONTENTS 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 General Description............................................................................................................................................... 4 PIC12C5XX Device Varieties ................................................................................................................................ 7 Architectural Overview..................................................................................
PIC12C5XX 1.0 GENERAL DESCRIPTION The PIC12C5XX from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static, EEPROM/EPROM/ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (1 µs) except for program branches which take two cycles. The PIC12C5XX delivers performance an order of magnitude higher than its competitors in the same price category.
PIC12C5XX TABLE 1-1: PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES PIC12C508(A) PIC12C509(A) PIC12CR509A PIC12CE518 PIC12CE519 PIC12C671 PIC12C672 PIC12CE673 PIC12CE674 Clock Memory Peripherals Features Maximum Frequency of Operation (MHz) 4 4 4 4 4 10 10 10 10 EPROM Program Memory 512 x 12 1024 x 12 1024 x 12 (ROM) 512 x 12 1024 x 12 1024 x 14 2048 x 14 1024 x 14 2048 x 14 RAM Data Memory (bytes) 25 41 41 25 41 128 128 128 128 EEPROM Data Memory (bytes) — — — 16 16 — —
PIC12C5XX NOTES: DS40139E-page 6 1999 Microchip Technology Inc.
PIC12C5XX 2.0 PIC12C5XX DEVICE VARIETIES A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC12C5XX Product Identification System at the back of this data sheet to specify the correct part number. 2.
PIC12C5XX NOTES: DS40139E-page 8 1999 Microchip Technology Inc.
PIC12C5XX 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC12C5XX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12C5XX uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus.
PIC12C5XX PIC12C5XX BLOCK DIAGRAM 12 GP0 GP1 GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP5/OSC1/CLKIN RAM 25 x 8 or 41 x 8 File Registers STACK1 STACK2 12 RAM Addr 9 Addr MUX Instruction reg Direct Addr 5 5-7 Indirect Addr FSR reg STATUS reg 8 3 OSC1/CLKIN OSC2 Timing Generation Internal RC OSC Power-on Reset Watchdog Timer 16 X 8 EEPROM Data Memory PIC12CE5XX Only MUX Device Reset Timer Instruction Decode & Control GPIO SDA Program Bus 8 Data Bus Program Counter ROM/EPROM 512 x 12 or 1024
PIC12C5XX TABLE 3-1: PIC12C5XX PINOUT DESCRIPTION DIP Pin # SOIC Pin # I/O/P Type GP0 7 7 I/O TTL/ST Bi-directional I/O port/ serial programming data. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. GP1 6 6 I/O TTL/ST Bi-directional I/O port/ serial programming clock. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change.
PIC12C5XX 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1.
PIC12C5XX MEMORY ORGANIZATION PIC12C5XX memory is organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. For the PIC12C509, PIC12C509A, PICCR509A and PIC12CE519 with a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR). 4.
PIC12C5XX 4.2 Data Memory Organization FIGURE 4-2: Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers.
PIC12C5XX 4.2.2 The special registers can be classified into two sets. The special function registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1).
PIC12C5XX 4.3 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bit for program memories larger than 512 words.
PIC12C5XX 4.4 OPTION Register Note: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin; i.e., note that TRIS overrides OPTION control of GPPU and GPWU. Note: If the T0CS bit is set to ‘1’, GP2 is forced to be an input even if TRIS GP2 = ‘0’. The OPTION register is a 8-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0.
PIC12C5XX 4.5 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains four to six bits for calibration. Increasing the cal value increases the frequency. See Section 7.2.5 for more information on the internal oscillator.
PIC12C5XX 4.6 Program Counter 4.6.1 EFFECTS OF RESET As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page i.e., the oscillator calibration instruction.
PIC12C5XX 4.8 Indirect Data Addressing; INDF and FSR Registers EXAMPLE 4-2: The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
PIC12C5XX 5.0 I/O PORT As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF GPIO,W) always read the I/O pins independent of the pin’s input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers are all set. See Section 7.0 for SCL and SDA description for PIC12CE5XX. 5.1 GPIO GPIO is an 8-bit I/O register. Only the low order 6 bits are used (GP5:GP0).
PIC12C5XX TABLE 5-1: Address N/A N/A SUMMARY OF PORT REGISTERS Name TRIS OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset Value on All Other Resets — — --11 1111 --11 1111 GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 GPWUF — PAO TO PD Z DC C 0001 1xxx q00q quuu(1) 03H STATUS 06h GPIO (PIC12C508/ PIC12C509/ PIC12C508A/ PIC12C509A/ PIC12CR509A) — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu 06h GPIO (PIC12CE518/ PIC
PIC12C5XX FIGURE 5-2: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched MOVWF GPIO PC + 1 MOVF GPIO,W Q1 Q2 Q3 Q4 PC + 2 PC + 3 This example shows a write to GPIO followed by a read from GPIO. NOP NOP Data setup time = (0.25 TCY – TPD) where: TCY = instruction cycle. GP5:GP0 TPD = propagation delay Port pin written here Instruction executed MOVWF GPIO (Write to GPIO) 1999 Microchip Technology Inc.
PIC12C5XX NOTES: DS40139E-page 24 1999 Microchip Technology Inc.
PIC12C5XX 6.0 TIMER0 MODULE AND TMR0 REGISTER Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1.
PIC12C5XX FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 Instruction Fetch T0 Timer0 PC PC+1 T0+1 T0+2 PC+4 PC+5 MOVF TMR0,W NT0 Write TMR0 executed Read TMR0 reads NT0 NT0+1 Read TMR0 reads NT0 PC+6 MOVF TMR0,W NT0+2 Read TMR0 reads NT0 + 1 Read TMR0 reads NT0 Read TMR0 reads NT0 + 2 TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
PIC12C5XX 6.1 Using Timer0 with an External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value.
PIC12C5XX 6.2 Prescaler EXAMPLE 6-1: An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT), respectively (Section 8.6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. 1.CLRWDT 2.CLRF TMR0 3.
PIC12C5XX 7.0 EEPROM PERIPHERAL OPERATION This section applies PIC12CE519 only. to PIC12CE518 and The PIC12CE518 and PIC12CE519 each have 16 bytes of EEPROM data memory. The EEPROM memory has an endurance of 1,000,000 erase/write cycles and a data retention of greater than 40 years. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol.
PIC12C5XX Figure 7-1: Block diagram of GPIO6 (SDA line) VDD reset To 24L00 SDA Pad D databus write GPIO ck EN Q Output Latch Q D Schmitt Trigger EN ck Input Latch ltchpin Read GPIO Figure 7-2: Block diagram of GPIO7 (SCL line) VDD To 24LC00 SCL Pad D databus write GPIO ck Q EN Q D Schmitt Trigger EN ck Read GPIO DS40139E-page 30 ltchpin 1999 Microchip Technology Inc.
PIC12C5XX 7.0.2 SERIAL CLOCK This SCL input is used to synchronize the data transfer from and to the device. 7.1 BUS CHARACTERISTICS The following bus protocol is to be used with the EEPROM data memory. • Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.
PIC12C5XX FIGURE 7-3: SCL (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (C) (D) START CONDITION ADDRESS OR ACKNOWLEDGE VALID (C) (A) SDA FIGURE 7-4: STOP CONDITION DATA ALLOWED TO CHANGE ACKNOWLEDGE TIMING Acknowledge Bit 1 SCL 2 SDA 3 4 5 6 7 8 9 1 Device Addressing After generating a START condition, the bus master transmits a control byte consisting of a slave address and a Read/Write bit that indicates what type of operation is to be performed.
PIC12C5XX 7.3 WRITE OPERATIONS 7.4 7.3.1 BYTE WRITE Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately.
PIC12C5XX 7.5 READ OPERATIONS device as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. It will then issue an acknowledge and transmits the eight bit data word.
PIC12C5XX 8.0 SPECIAL FEATURES OF THE CPU The PIC12C5XX has a Watchdog Timer which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using XT or LP selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal oscillator is stable. If using INTRC or EXTRC there is an 18 ms delay only on VDD power-up.
PIC12C5XX 8.2 Oscillator Configurations 8.2.1 OSCILLATOR TYPES TABLE 8-1: The PIC12C5XX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1:FOSC0) to select one of these four modes: • • • • LP: XT: INTRC: EXTRC: 8.2.2 Low Power Crystal Crystal/Resonator Internal 4 MHz Oscillator External Resistor/Capacitor Osc Type CRYSTAL OPERATION (OR CERAMIC RESONATOR) (XT OR LP OSC CONFIGURATION) C1(1) OSC1 Cap. Range C1 Cap. Range C2 XT 4.
PIC12C5XX 8.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance.
PIC12C5XX 8.2.5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25°C, see “Electrical Specifications” section for information on variation over voltage and temperature. In addition, a calibration instruction is programmed into the top of memory which contains the calibration value for the internal RC oscillator. This location is never code protected regardless of the code protect settings.
PIC12C5XX TABLE 8-3: RESET CONDITIONS FOR REGISTERS Address Power-on Reset MCLR Reset WDT time-out Wake-up on Pin Change W (PIC12C508/509) — qqqq xxxx (1) qqqq uuuu (1) W (PIC12C508A/509A/ PIC12CE518/519/ PIC12CE509A) — qqqq qqxx (1) qqqq qquu (1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 STATUS 03h 0001 1xxx 1111 1111 q00q quuu (2,3) FSR (PIC12C508/ PIC12C508A/ PIC12CE518) 04h 111x xxxx 111u uuuu FSR (PIC12C509/ PIC12C509A/ PIC12CE519/ PIC12CR
PIC12C5XX 8.3.1 MCLR ENABLE This configuration bit when unprogrammed (left in the ‘1’ state) enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD, and the pin is assigned to be a GPIO. See Figure 8-7. When pin GP3/MCLR/VPP is configured as MCLR, the internal pull-up is always on. FIGURE 8-7: MCLR SELECT MCLRE WEAK PULL-UP GP3/MCLR/V PP 8.
PIC12C5XX FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Power-Up Detect POR (Power-On Reset) VDD Pin Change Wake-up on pin change SLEEP GP3/MCLR/VPP WDT Time-out MCLRE RESET 8-bit Asynch On-Chip DRT OSC S Q R Q Ripple Counter (Start-Up Timer) CHIP RESET FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR INTERNAL POR TDRT
PIC12C5XX FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min. 8.5 Device Reset Timer (DRT) In the PIC12C5XX, DRT runs from RESET and varies based on oscillator selection (see Table 8-5.) The DRT operates on an internal RC oscillator.
PIC12C5XX 8.6.1 WDT PERIOD 8.6.2 The WDT has a nominal time-out period of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-topart process variations (see DC specs).
PIC12C5XX 8.7 Time-Out Sequence, Power Down, and Wake-up from SLEEP Status Bits (TO/PD/GPWUF) FIGURE 8-14: BROWN-OUT PROTECTION CIRCUIT 2 VDD The TO, PD, and GPWUF bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) reset.
PIC12C5XX 8.9 Power-Down Mode (SLEEP) A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). 8.9.1 SLEEP The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low, or hi-impedance).
PIC12C5XX 8.12 In-Circuit Serial Programming The PIC12C5XX microcontrollers with EPROM program memory can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product.
PIC12C5XX 9.0 INSTRUCTION SET SUMMARY Each PIC12C5XX instruction is a 12-bit word divided into an OPCODE, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The PIC12C5XX instruction set summary in Table 9-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. Table 9-1 shows the opcode field descriptions.
PIC12C5XX TABLE 9-2: INSTRUCTION SET SUMMARY Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f,d f,d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d 12-Bit Opcode Description Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through Carry Rotate right f through Carry Subtract
PIC12C5XX ADDWF Add W and f Syntax: [ label ] ADDWF Operands: Operation: ANDWF [ label ] ANDWF 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] (W) + (f) → (dest) Operation: (W) .AND. (f) → (dest) Status Affected: C, DC, Z Encoding: 0001 Description: AND W with f Syntax: f,d f,d Status Affected: Z 11df ffff Encoding: 0001 01df ffff Add the contents of the W register and register ’f’. If ’d’ is 0 the result is stored in the W register.
PIC12C5XX BSF Bit Set f Syntax: [ label ] BSF BTFSS Operands: Operation: Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b 0 ≤ f ≤ 31 0≤b≤7 Operands: 0 ≤ f ≤ 31 0≤b<7 1 → (f) Operation: skip if (f) = 1 f,b Status Affected: None Encoding: Status Affected: None 0101 bbbf ffff Description: Bit ’b’ in register ’f’ is set.
PIC12C5XX CALL Subroutine Call CLRW Syntax: [ label ] CALL k Syntax: [ label ] CLRW Operands: 0 ≤ k ≤ 255 Operands: None Operation: (PC) + 1→ Top of Stack; k → PC<7:0>; (STATUS<6:5>) → PC<10:9>; 0 → PC<8> Operation: 00h → (W); 1→Z Status Affected: None Encoding: Description: 1001 kkkk kkkk Subroutine call. First, return address (PC+1) is pushed onto the stack. The eight bit immediate address is loaded into PC bits <7:0>.
PIC12C5XX COMF Complement f Syntax: [ label ] COMF Operands: Operation: DECFSZ [ label ] DECFSZ f,d 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] (f) → (dest) Operation: (f) – 1 → d; Encoding: 0010 01df ffff Description: The contents of register ’f’ are complemented. If ’d’ is 0 the result is stored in the W register. If ’d’ is 1 the result is stored back in register ’f’.
PIC12C5XX INCF Increment f IORLW Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (f) + 1 → (dest) (W) .OR. (k) → (W) Operation: INCF f,d Description: Words: Encoding: 0010 10df ffff The contents of register ’f’ are incremented. If ’d’ is 0 the result is placed in the W register. If ’d’ is 1 the result is placed back in register ’f’.
PIC12C5XX MOVF Move f Syntax: [ label ] MOVWF Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) → (dest) MOVF f,d 0010 Description: [ label ] Operands: 0 ≤ f ≤ 31 Operation: (W) → (f) Encoding: 00df ffff The contents of register ’f’ is moved to destination ’d’. If ’d’ is 0, destination is the W register. If ’d’ is 1, the destination is file register ’f’. ’d’ is 1 is useful to test a file register since status flag Z is affected.
PIC12C5XX OPTION Load OPTION Register RLF Syntax: [ label ] Syntax: [ label ] RLF Operands: None Operands: Operation: (W) → OPTION 0 ≤ f ≤ 31 d ∈ [0,1] Operation: See description below OPTION Status Affected: None Encoding: 0000 Description: 0000 0010 The content of the W register is loaded into the OPTION register.
PIC12C5XX SLEEP Enter SLEEP Mode SUBWF Subtract W from f Syntax: [label] Syntax: [label] Operands: None Operands: Operation: 00h → WDT; 0 → WDT prescaler; 1 → TO; 0 → PD 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) – (W) → (dest) SLEEP Status Affected: TO, PD, GPWUF Status Affected: C, DC, Z Encoding: 0000 10df ffff Description: Subtract (2’s complement method) the W register from register 'f'. If 'd' is 0 the result is stored in the W register.
PIC12C5XX SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [label] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 (f<3:0>) → (dest<7:4>); (f<7:4>) → (dest<3:0>) Operation: Operation: (W) .XOR. k → (W) Status Affected: Z Encoding: Status Affected: None XORLW k 1111 kkkk kkkk Description: The upper and lower nibbles of register ’f’ are exchanged. If ’d’ is 0 the result is placed in W register.
PIC12C5XX NOTES: DS40139E-page 58 1999 Microchip Technology Inc.
PIC12C5XX 10.0 DEVELOPMENT SUPPORT 10.
PIC12C5XX 10.6 SIMICE Entry-Level Hardware Simulator SIMICE is an entry-level hardware development system designed to operate in a PC-based environment with Microchip’s simulator MPLAB™-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology’s MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware simulation for Microchip’s PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicro 8-bit microcontrollers.
PIC12C5XX 10.10 MPLAB Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: • A full featured editor • Three operating modes - editor - emulator - simulator • A project manager • Customizable tool bar and key mapping • A status bar with project information • Extensive on-line help 10.
PIC12C5XX 10.16 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters. DS40139E-page 62 1999 Microchip Technology Inc.
1999 Microchip Technology Inc. Emulator Products Software Tools á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á á KEELOQ Transponder Kit á KEELOQ® Evaluation Kit PICDEM-3 á PICDEM-2 á PICDEM-1 á PICDEM-14A á á SIMICE HCS200 HCS300 HCS301 á SEEVAL Designers Kit á á KEELOQ Programmer 24CXX 25CXX 93CXX á PRO MATE II Universal Programmer á PICSTARTPlus Low-Cost Universal Dev.
PIC12C5XX NOTES: DS40139E-page 64 1999 Microchip Technology Inc.
PIC12C5XX 11.0 ELECTRICAL CHARACTERISTICS - PIC12C508/PIC12C509 Absolute Maximum Ratings† Ambient Temperature under bias ........................................................................................................... –40°C to +125°C Storage Temperature ............................................................................................................................. –65°C to +150°C Voltage on VDD with respect to VSS ....................................................................
PIC12C5XX 11.1 DC CHARACTERISTICS: PIC12C508/509 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) –40°C ≤ TA ≤ +125°C (extended) DC Characteristics Power Supply Pins Parm No. Characteristic Sym Min 2.5 Typ(1) Max Units 5.5 V 5.
PIC12C5XX 11.2 DC CHARACTERISTICS: PIC12C508/509 (Commercial, Industrial, Extended) DC CHARACTERISTICS Param No. Characteristic Input Low Voltage I/O ports with TTL buffer D030 D031 D032 D033 Standard Operating Conditions (unless otherwise specified) Operating temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) –40°C ≤ TA ≤ +125°C (extended) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.2.
PIC12C5XX TABLE 11-1: VDD (Volts) PULL-UP RESISTOR RANGES - PIC12C508/C509 Temperature (°C) Min Typ Max Units 42K 48K 49K 55K 17K 20K 22K 24K 63K 63K 63K 63K 20K 23K 25K 28K Ω Ω Ω Ω Ω Ω Ω Ω 346K 414K 457K 504K 292K 341K 371K 407K 417K 532K 532K 593K 360K 437K 448K 500K Ω Ω Ω Ω Ω Ω Ω Ω GP0/GP1 2.5 5.5 –40 25 85 125 –40 25 85 125 38K 42K 42K 50K 15K 18K 19K 22K –40 25 85 125 –40 25 85 125 285K 343K 368K 431K 247K 288K 306K 351K GP3 2.5 5.
PIC12C5XX 11.3 Timing Parameter Symbology and Load Conditions - PIC12C508/C509 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC12C5XX 11.4 Timing Diagrams and Specifications FIGURE 11-2: EXTERNAL CLOCK TIMING - PIC12C508/C509 Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 TABLE 11-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12C508/C509 AC Characteristics Parameter No. Sym FOSC Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial), –40°C ≤ TA ≤ +85°C (industrial), –40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 11.
PIC12C5XX TABLE 11-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508/C509 AC Characteristics Parameter No. Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial), –40°C ≤ TA ≤ +85°C (industrial), –40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 Min* Typ(1) Internal Calibrated RC Frequency 3.58 4.00 4.32 MHz VDD = 5.0V Internal Calibrated RC Frequency 3.50 — 4.26 MHz VDD = 2.
PIC12C5XX TABLE 11-4: TIMING REQUIREMENTS - PIC12C508/C509 AC Characteristics Parameter No. Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) –40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 11.
PIC12C5XX TABLE 11-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) –40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 11.1 Parameter No.
PIC12C5XX FIGURE 11-5: TIMER0 CLOCK TIMINGS - PIC12C508/C509 T0CKI 40 41 42 TABLE 11-7: TIMER0 CLOCK REQUIREMENTS - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) –40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 11.1. Parameter Sym Characteristic No.
PIC12C5XX 12.0 DC AND AC CHARACTERISTICS - PIC12C508/PIC12C509 The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time.
PIC12C5XX TABLE 12-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C Oscillator Frequency VDD = 2.5V External RC 4 MHz 250 µA* Internal RC 4 MHz 420 µA XT 4 MHz 251 µA LP 32 KHz 15 µA *Does not include current through external R&C. FIGURE 12-3: WDT TIMER TIME-OUT PERIOD VS. VDD VDD = 5.5V 780 µA* 1.1 mA 780 µA 37 µA FIGURE 12-4: SHORT DRT PERIOD VS.
PIC12C5XX FIGURE 12-5: IOH vs. VOH, VDD = 2.5 V FIGURE 12-7: IOL vs. VOL, VDD = 2.5 V 25 0 -1 20 Max –40°C 15 -3 IOL (mA) IOH (mA) -2 -4 Min + -5 -6 Typ +25°C 10 125 °C Min +85°C 85°C Min + Min +125°C 5 Typ +25°C C Max –40° -7 500m 1.0 1.5 2.0 2.5 0 VOH (Volts) 0 250.0m 500.0m 1.0 VOL (Volts) FIGURE 12-6: IOH vs. VOH, VDD = 5.5 V FIGURE 12-8: IOL vs. VOL, VDD = 5.
PIC12C5XX NOTES: DS40139E-page 78 1999 Microchip Technology Inc.
PIC12C5XX 13.0 ELECTRICAL CHARACTERISTICS - PIC12C508A/PIC12C509A/ PIC12LC508A/PIC12LC509A/PIC12CR509A/PIC12CE518/PIC12CE519/ PIC12LCE518/PIC12LCE519/PIC12LCR509A Absolute Maximum Ratings† Ambient Temperature under bias ........................................................................................................... –40°C to +125°C Storage Temperature .............................................................................................................................
PIC12C5XX 13.1 DC CHARACTERISTICS: PIC12C508A/509A (Commercial, Industrial, Extended) PIC12CE518/519 (Commercial, Industrial, Extended) PIC12CR509A (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) –40°C ≤ TA ≤ +125°C (extended) DC Characteristics Power Supply Pins Parm No. Characteristic Sym Min 3.0 Typ(1) Max Units Conditions 5.
PIC12C5XX 13.2 DC CHARACTERISTICS: PIC12LC508A/509A (Commercial, Industrial) PIC12LCE518/519 (Commercial, Industrial) PIC12LCR509A (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) DC Characteristics Power Supply Pins Parm No. Characteristic Sym Min Typ(1) Max Units 2.
PIC12C5XX 13.3 DC CHARACTERISTICS: DC CHARACTERISTICS Param No.
PIC12C5XX 13.4 DC CHARACTERISTICS: DC CHARACTERISTICS Param No.
PIC12C5XX TABLE 13-1: VDD (Volts) PULL-UP RESISTOR RANGES* - PIC12C508A, PIC12C509A, PIC12CR509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 Temperature (°C) Min Typ Max Units 42K 48K 49K 55K 17K 20K 22K 24K 63K 63K 63K 63K 20K 23K 25K 28K Ω Ω Ω Ω Ω Ω Ω Ω 346K 414K 457K 504K 292K 341K 371K 407K 417K 532K 532K 593K 360K 437K 448K 500K Ω Ω Ω Ω Ω Ω Ω Ω GP0/GP1 2.5 5.
PIC12C5XX 13.5 Timing Parameter Symbology and Load Conditions - PIC12C508A, PIC12C509A, PIC12CR509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC12C5XX 13.6 Timing Diagrams and Specifications FIGURE 13-2: EXTERNAL CLOCK TIMING - PIC12C508A, PIC12C509A, PIC12CR509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 TABLE 13-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 AC Characteristics Parameter No.
PIC12C5XX TABLE 13-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 AC Characteristics Parameter No. Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial), –40°C ≤ TA ≤ +85°C (industrial), –40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 10.1 Min* Typ(1) Internal Calibrated RC Frequency 3.65 4.00 4.
PIC12C5XX FIGURE 13-3: I/O TIMING - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 Q1 Q4 Q2 Q3 OSC1 I/O Pin (input) 17 I/O Pin (output) 18 19 New Value Old Value 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
PIC12C5XX FIGURE 13-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 VDD MCLR 30 Internal POR 32 32 32 DRT Timeout (Note 2) Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT reset only in XT and LP modes.
PIC12C5XX TABLE 13-6: DRT (DEVICE RESET TIMER PERIOD) - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 Oscillator Configuration IntRC & ExtRC POR Reset Subsequent Resets (1) 300 µs (typical)(1) (1) 18 ms (typical)(1) 18 ms (typical) XT & LP 18 ms (typical) Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
PIC12C5XX TABLE 13-8: EEPROM MEMORY BUS TIMING REQUIREMENTS - PIC12CE5XX ONLY. AC Characteristics Parameter Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C, Vcc = 3.0V to 5.5V (commercial) –40°C ≤ TA ≤ +85°C, Vcc = 3.0V to 5.5V (industrial) –40°C ≤ TA ≤ +125°C, Vcc = 4.5V to 5.5V (extended) Operating Voltage VDD range is described in Section 13.1 Symbol Min Max Units Clock frequency FCLK — — — 100 100 400 kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range) 3.
PIC12C5XX NOTES: DS40139E-page 92 1999 Microchip Technology Inc.
PIC12C5XX 14.0 DC AND AC CHARACTERISTICS - PIC12C508A/PIC12C509A/ PIC12LC508A/PIC12LC509A, PIC12CE518/PIC12CE519/PIC12CR509A/ PIC12LCE518/PIC12LCE519/ PIC12LCR509A The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range.
PIC12C5XX TABLE 14-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C Oscillator Frequency VDD =3.0V External RC 4 MHz 240 µA* Internal RC 4 MHz 320 µA XT 4 MHz 300 µA LP 32 KHz 19 µA *Does not include current through external R&C. 800 µA* 800 µA 800 µA 50 µA FIGURE 14-4: TYPICAL IDD VS. FREQUENCY (WDT DIS, 25°C, VDD = 5.5V) 600 600 550 550 500 500 450 450 400 400 350 350 IDD (µA) IDD (µA) FIGURE 14-3: TYPICAL IDD VS. VDD (WDT DIS, 25°C, FREQUENCY = 4MHZ) VDD = 5.
PIC12C5XX FIGURE 14-7: IOH vs. VOH, VDD = 2.5 V FIGURE 14-5: WDT TIMER TIME-OUT PERIOD vs. VDD 55 -0 50 -1 -2 45 -3 -4 35 Max +125°C IOH (mA) WDT period (µS) 40 30 Min +125°C Min +85°C -5 -6 Typ +25°C Max +85°C -7 25 -8 20 Typ +25°C -9 15 Max -40°C -10 MIn –40°C .5 .75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 10 0 2.5 3.5 4.5 5.5 VOH (Volts) 6.5 VDD (Volts) FIGURE 14-6: SHORT DRT PERIOD VS. VDD FIGURE 14-8: IOH vs. VOH, VDD = 3.
PIC12C5XX FIGURE 14-9: IOL vs. VOL, VDD = 2.5 V FIGURE 14-11: IOH vs. VOH, VDD = 5.5 V 35 0 -5 30 Max -40°C -10 25 20 Typ +25°C IOH (mA) IOL (mA) -15 15 Mi n+ C 5° 12 °C 85 n+ Mi °C 25 p+ Ty -20 -25 10 –4 0° C Min +85°C M ax -30 Min +125°C 5 -35 -40 0 0 0.25 0.5 0.75 3.5 1.0 4.0 4.5 5.0 5.5 VOH (Volts) VOL (Volts) FIGURE 14-12: IOL vs. VOL, VDD = 5.5 V FIGURE 14-10: IOL vs. VOL, VDD = 3.
PIC12C5XX FIGURE 14-13: TYPICAL IPD VS. VDD, WATCHDOG DISABLED (25°C) 1.8 250 1.6 VTH (Volts) 260 240 Ipd (nA) FIGURE 14-14: VTH (INPUT THRESHOLD VOLTAGE) OF GPIO PINS VS. VDD Max (-40 to 125) 1.4 230 1.2 220 1.0 210 0.8 Typ (25) Min (-40 to 125) 200 2.5 0.6 3.0 3.5 4.5 VDD (Volts) 5.0 5.5 0 2.5 3.5 4.5 5.5 VDD (Volts) 1999 Microchip Technology Inc.
PIC12C5XX FIGURE 14-15: VIL, VIH OF NMCLR, AND T0CKI VS. VDD 3.5 Vih Max (-40 to 125) VIH Typ (25) VIH Min (-40 to 125) VIL, VIH (Volts) 3.0 2.5 2.0 VIL Max (-40 to 125) 1.5 VIL Typ (25) VIL Min (-40 to 125) 1.0 0.5 2.5 3.5 4.5 5.5 VDD (Volts) DS40139E-page 98 1999 Microchip Technology Inc.
PIC12C5XX 15.0 PACKAGING INFORMATION 15.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXCDE AABB 12C508A 04I/PSAZ 9825 8-Lead SOIC (150 mil) XXXXXXX 9825 8-Lead SOIC (208 mil) XXXXXXX XXXXXXX AABBCDE Example 12C508A 04I/SM 9824SAZ 8-Lead Windowed Ceramic Side Brazed (300 mil) Example JW XXX 12C508A XXXXXX Legend: MM...M XX...
PIC12C5XX Package Type: K04-018 8-Lead Plastic Dual In-line (P) – 300 mil E D 2 1 n α E1 A A1 R L c A2 β B1 p eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom B INCHES* NOM 0.300 8 0.100 0.018 0.014 0.
PIC12C5XX Package Type: K04-057 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil E1 E p D 2 B n 1 α X 45 ° L R2 c A φ R1 β Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Chamfer Distance Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom L1 A2 INCHES* NOM 0.050 8 0.054 0.061 0.027 0.035 0.
PIC12C5XX Package Type: K04-056 8-Lead Plastic Small Outline (SM) – Medium, 208 mil E1 E p D 2 n 1 B α L R2 c A φ R1 L1 β Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom INCHES* NOM 0.050 8 0.070 0.074 0.037 0.042 0.005 0.002 0.200 0.205 0.203 0.
PIC12C5XX Package Type: K04-084 8-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil E W T D 2 n 1 U A A1 L A2 c B1 p eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Lead Thickness Top to Seating Plane Top of Body to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Package Width Overall Row Spacing Window Diameter Lid Length Lid Width B MIN n p B B1 c A A1 A2 L D E eB W T U 0.098 0.016 0.050 0.008 0.145 0.
PIC12C5XX NOTES: DS40139E-page 104 1999 Microchip Technology Inc.
PIC12C5XX INDEX A ALU ....................................................................................... 9 Applications........................................................................... 4 Architectural Overview .......................................................... 9 Assembler MPASM Assembler..................................................... 61 B Block Diagram On-Chip Reset Circuit ................................................. 41 Timer0..............................................
PIC12C5XX DS40139E-page 106 1999 Microchip Technology Inc.
PIC12C5XX ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
PIC12C5XX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
PIC12C5XX PIC12C5XX Product Identification System Examples PART NO.
PIC12C5XX NOTES: DS40139E-page 110 1999 Microchip Technology Inc.
PIC12C5XX NOTES: 1999 Microchip Technology Inc.
Note the following details of the code protection feature on PICmicro® MCUs. • • • • • • The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature.
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