Datasheet

PIC10(L)F320/322
DS41585A-page 182 Preliminary  2011 Microchip Technology Inc.
FIGURE 24-7: RESET, WATCHDOG TIMER, AND POWER-UP TIMER TIMING
FIGURE 24-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
Internal Reset
(1)
Watchdog Timer
33
30
31
34
I/O pins
34
Note 1: Asserted low.
Reset
(1)
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
33
(1)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
Reset
(due to BOR)
V
BOR and VHYST
37