Datasheet

 2011 Microchip Technology Inc. Preliminary DS41585A-page 181
PIC10(L)F320/322
FIGURE 24-6: CLKR AND I/O TIMING
TABLE 24-3: CLKR AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C T
A +125°C
Param
No.
Sym. Characteristic Min. Typ† Max. Units Conditions
OS11 TosH2ckL F
OSC to CLKR
(1)
——70nsVDD = 3.3-5.0V
OS12 TosH2ckH F
OSC to CLKR
(1)
——72nsVDD = 3.3-5.0V
OS13 TckL2ioV CLKR to Port out valid
(1)
——20ns
OS14 TioV2ckH Port input valid before CLKR
(1)
TOSC + 200 ns — — ns
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns V
DD = 3.3-5.0V
OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid
(I/O in hold time)
50 — — ns VDD = 3.3-5.0V
OS17 TioV2osH Port input valid to Fosc(Q2 cycle)
(I/O in setup time)
20 — — ns
OS18 TioR Port output rise time —
—
40
15
72
32
ns V
DD = 1.8V
V
DD = 3.3-5.0V
OS19 TioF Port output fall time —
—
28
15
55
30
ns VDD = 1.8V
V
DD = 3.3-5.0V
OS20* Tinp INT pin input high or low time 25 — — ns
OS21* Tioc Interrupt-on-change new input level
time
25 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in EC mode where CLKR output is 4 x T
OSC.
FOSC
CLKR
I/O pin
(Input)
I/O pin
(Output)
Q4
Q1
Q2 Q3
OS11
OS19
OS13
OS15
OS18, OS19
OS20
OS21
OS17
OS16
OS14
OS12
OS18
Old Value
New Value
Write Fetch Read ExecuteCycle