Datasheet

 2011 Microchip Technology Inc. Preliminary DS41585A-page 119

PIC10(L)F320/322

19.5 CLC Control Registers

R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

LCxEN LCxOE LCxOUT LCxINTP LCxINTN LCxMODE<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxEN: Configurable Logic Cell Enable bit

1 = Configurable Logic Cell is enabled and mixing input signals

0 = Configurable Logic Cell is disabled and has logic zero output

bit 6 LCxOE: Configurable Logic Cell Output Enable bit

1 = Configurable Logic Cell port pin output enabled

0 = Configurable Logic Cell port pin output disabled

bit 5 LCxOUT: Configurable Logic Cell Data Output bit

Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire.

bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit

1 = CLCxIF will be set when a rising edge occurs on lcx_out

0 = CLCxIF will not be set

bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit

1 = CLCxIF will be set when a falling edge occurs on lcx_out

0 = CLCxIF will not be set

bit 2-0 LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits

111 = Cell is 1-input transparent latch with S and R

110 = Cell is J-K Flip-Flop with R

101 = Cell is 2-input D Flip-Flop with R

100 = Cell is 1-input D Flip-Flop with S and R

011 = Cell is S-R latch

010 = Cell is 4-input AND

001 =Cell is OR-XOR

000 = Cell is AND-OR