Datasheet

PIC10(L)F320/322
DS41585A-page 114 Preliminary  2011 Microchip Technology Inc.
19.1 CLCx Setup
Programming the CLCx module is performed by config-
uring the four stages in the logic signal flow. The four
stages are:
•Data selection
• Data gating
• Logic function selection
• Output polarity
Each stage is setup at run time by writing to the corre-
sponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
19.1.1 DATA SELECTION
There are eight signals available as inputs to the con-
figurable logic. Four 8-input multiplexers are used to
select the inputs to pass on to the next stage.
Data inputs are selected with the CLCxSEL0 and
CLCxSEL1 registers (Register 19-3 and Register 19-4,
respectively).
Data selection is through four multiplexers as indicated
on the left side of Figure 19-2. Data inputs in the figure
are identified by a generic numbered input name.
Table 19-1 correlates the generic input name to the
actual signal for each CLC module. The columns
labeled lcxd1 through lcxd4 indicate the MUX output for
the selected data input. D1S through D4S are
abbreviations for the MUX select input codes:
LCxD1S<2:0> through LCxD4S<2:0>, respectively.
Selecting a data input in a column excludes all other
inputs in that column.
19.1.2 DATA GATING
Outputs from the input multiplexers are directed to the
desired logic function input through the data gating
stage. Each data gate can direct any combination of the
four selected inputs.
The gate stage is more than just signal direction. The gate
can be configured to direct each input signal as inverted
or non-inverted data. Directed signals are ANDed
together in each gate. The output of each gate can be
inverted before going on to the logic function stage.
The gating is in essence a 1-to-4 input AND/NAND/OR/
NOR gate. When every input is inverted and the output
is inverted, the gate is an OR of all enabled data inputs.
When the inputs and output are not inverted, the gate
is an AND or all enabled inputs.
Table 19-2 summarizes the basic logic that can be
obtained in gate 1 by using the gate logic select bits.
The table shows the logic of four input variables, but
each gate can be configured to use less than four. If no
inputs are selected, the output will be zero or one,
depending on the gate output polarity bit.
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses). If
the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select
registers as follows:
• Gate 1: CLCxGLS0 (Register 19-5)
• Gate 2: CLCxGLS1 (Register 19-6)
• Gate 3: CLCxGLS2 (Register 19-7)
• Gate 4: CLCxGLS3 (Register 19-8)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.
Data gating is indicated in the right side of Figure 19-2.
Only one gate is shown in detail. The remaining three
gates are configured identically with the exception that
the data enables correspond to the enables for that gate.
Note: Data selections are undefined at power-up.
TABLE 19-1: CLCx DATA INPUT
SELECTION
Data Input
lcxd1
D1S
lcxd2
D2S
lcxd3
D3S
lcxd4
D4S
CLC 1
CLCxIN[0] 000 000 000 000 CLCx
CLCxIN[1]
001 001 001 001 CLCxIN1
CLCxIN[2]
010 010 010 010 CLCxIN2
CLCxIN[3]
011 011 011 011 PWM1
CLCxIN[4]
100 100 100 100 PWM2
CLCxIN[5]
101 101 101 101 NCOx
CLCxIN[6]
110 110 110 110 FOSC
CLCxIN[7] 111 111 111 111 LFINTOSC
Note: Data gating is undefined at power-up.
TABLE 19-2: DATA GATING LOGIC
CLCxGLS0 LCxGyPOL Gate Logic
0x55 1 AND
0x55 0 NAND
0xAA 1 NOR
0xAA 0 OR
0x00 0 Logic 0
0x00 1 Logic 1