Datasheet

 2011 Microchip Technology Inc. Preliminary DS41585A-page 113
PIC10(L)F320/322
19.0 CONFIGURABLE LOGIC CELL
(CLC)
The Configurable Logic Cell (CLCx) provides program-
mable logic that operates outside the speed limitations
of software execution. The logic cell selects any combi-
nation of the eight input signals and through the use of
configurable gates reduces the selected inputs to four
logic lines that drive one of eight selectable single-out-
put logic functions.
Input sources are a combination of the following:
• Two I/O pins
• Internal clocks
• Peripherals
• Register bits
The output can be directed internally to peripherals and
to an output pin.
Refer to Figure 19-1 for a simplified diagram showing
signal flow through the CLCx.
Possible configurations include:
• Combinatorial Logic
-AND
-NAND
- AND-OR
- AND-OR-INVERT
-OR-XOR
-OR-XNOR
• Latches
-S-R
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
FIGURE 19-1: CLCx SIMPLIFIED BLOCK DIAGRAM
lcxg1
lcxg2
lcxg3
lcxg4
Interrupt
det
Logic
Function
Input Data Selection Gates
CLCx
LCxOE
lcxq
LCxPOL
LCxOUT
DQ
LE
Q1
LCxMODE<2:0>
lcx_out
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
TRIS Control
Interrupt
det
LCxINTP
LCxINTN
CLCxIF
sets
LCxEN
See Figure 19-2
flag
See Figure 19-3