PIC10(L)F320/322 Data Sheet 6/8-Pin, High-Performance, Flash Microcontrollers 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC10(L)F320/322 6/8-Pin Flash-Based, 8-Bit Microcontrollers High-Performance RISC CPU: Low-Power Features (PIC10LF320/322): • Only 35 Instructions to Learn: - All single-cycle instructions, except branches • Operating Speed: - DC – 16 MHz clock input - DC – 250 ns instruction cycle • Up to 512 Words of Flash Program Memory • 64 Bytes Data Memory • Eight-level Deep Hardware Stack • Interrupt Capability • Processor Self-Write/Read access to Program Memory • Pinout Compatible to other 6-Pin PIC10FXXX Microc
PIC10(L)F320/322 TABLE 1: PIC10(L)F320/322 FEATURE SUMMARY Program Memory Flash (words) SRAM (bytes) I/O(1) PIC10F320 256 64 4 PIC10LF320 256 64 4 3 1 2 2 1 1 PIC10F322 512 64 4 3 1 2 2 1 1 PIC10LF322 512 64 4 3 1 2 2 1 1 Basic ICSP Device 8-bit A/D (ch) CLC 3 10-bit PWM Timers 8-bit NCO CWG 2 2 1 1 1 Note 1: One pin is input-only.
PIC10(L)F320/322 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Memory Organization ................................................................................................................................................................. 11 3.0 Device Configuration ......................................................................
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PIC10(L)F320/322 1.0 DEVICE OVERVIEW The PIC10(L)F320/322 are described within this data sheet. They are available in 6/8-pin packages. Figure 1-1 shows a block diagram of the PIC10(L)F320/322 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device.
PIC10(L)F320/322 FIGURE 1-1: PIC10(L)F320/322 BLOCK DIAGRAM Program Flash Memory RAM CLKR PORTA Timing Generation CLKIN CPU INTRC Oscillator Figure 2-1 MCLR Timer0 Temp. Indicator Note DS41585A-page 8 1: ADC 8-Bit Timer2 FVR PWM1 PWM2 NCO CLC CWG See applicable chapters for more information on peripherals. Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 TABLE 1-2: PIC10(L)F320/322 PINOUT DESCRIPTION Name RA0/PWM1/CLC1IN1/CWG1A/ AN0/ICSPDAT RA1/PWM2/CLC1/CWG1B/AN1/ CLKIN/ICSPCLK/NCO1CLK RA2/INT/T0CKI/NCO1/CLC1IN2/ CLKR/AN2/CWG1FLT RA3/MCLR/VPP Function Input Type RA0 TTL PWM1 — CLC1IN1 ST CWG1A — Output Type Description CMOS General purpose I/O with IOC and WPU. CMOS PWM output. — CLC input. CMOS CWG primary output. AN0 AN ICSPDAT ST CMOS ICSP™ Data I/O. — A/D Channel input.
PIC10(L)F320/322 NOTES: DS41585A-page 10 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The mid-range core has a 13-bit program counter capable of addressing 8K x 14 program memory space. This device family only implements up to 512 words of the 8K program memory space. Table 2-1 shows the memory sizes implemented for the PIC10(L)F320/322 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space.
PIC10(L)F320/322 FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR PIC10(L)F320 FIGURE 2-2: PROGRAM MEMORY MAP AND STACK FOR PIC10(L)F322 PC<12:0> PC<12:0> CALL, RETURN, RETLW RETFIE On-chip Program Memory 13 13 Stack Level 0 Stack Level 1 Stack Level 0 Stack Level 1 Stack Level 8 Stack Level 8 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 Rollover to Page 0 Wraps to Page 0 00FFh 0100h On-chip Program Memory Page 0 Wraps to Page 0
PIC10(L)F320/322 2.2 2.2.1 Data Memory Organization The data memory is in one bank, which contains the General Purpose Registers (GPR) and the Special Function Registers (SFR). The RP<1:0> bits of the STATUS register are the bank select bits. RP1 0 RP0 0 Bank 0 is selected The bank extends up to 7Fh (128 bytes). The lower locations of the bank are reserved for the Special Function Registers. Above the Special Function Registers are the General Purpose Registers, implemented as Static RAM.
PIC10(L)F320/322 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC10(L)F320/322 REGISTER 2-1: STATUS: STATUS REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R-1/q R-1/q R/W-x/u R/W-x/u R/W-x/u IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 IRP: Reserved(2) bit 6-5 RP<1:0>: Reserved(2) bit 4 TO: Time-out bit 1 = After p
PIC10(L)F320/322 2.2.3 DEVICE MEMORY MAPS The memory maps for PIC10(L)F320/322 are as shown in Table 2-2.
PIC10(L)F320/322 TABLE 2-3: Address SPECIAL FUNCTION REGISTER SUMMARY (BANK 0) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 02h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 03h STATUS 0001 1xxx 000q quuu 04h FSR 05h POR
PIC10(L)F320/322 TABLE 2-3: Address SPECIAL FUNCTION REGISTER SUMMARY (BANK 0) (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 — — — — Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets 0000 0000 0000 0000 — — PMADR8 ---- ---0 ---- ---0 Bank 0 (Continued) 20h PMADRL 21h PMADRH PMADR<7:0> 22h PMDATL 23h PMDATH — — 24h PMCON1 — CFGS 25h PMCON2 26h CLKRCON — PMDAT<7:0> PMDAT<13:8> LWLO FREE WRERR WREN WR RD Program Memory Control Register 2 (not a phy
PIC10(L)F320/322 2.3 2.3.2 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
PIC10(L)F320/322 FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC10(L)F320/322 Direct Addressing 6 From Opcode Indirect Addressing 0 7 File Select Register 0 Location Select Location Select 00h Data Memory 7Fh Bank 0 For memory map detail, see Figure 2-2. DS41585A-page 20 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 3.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Word and Device ID. 3.1 Configuration Word There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word at 2007h. 2011 Microchip Technology Inc.
PIC10(L)F320/322 REGISTER 3-1: CONFIG: CONFIGURATION WORD U-1 R/P-1/1 — R/P-1/1 WRT<1:0> R/P-1/1 R/P-1/1 R/P-1/1 BORV LPBOR LVP bit 13 R/P-1/1 R/P-1/1 R/P-1/1 CP MCLRE PWRTE bit 8 R/P-1/1 R/P-1/1 R/P-1/1 WDTE<1:0> R/P-1/1 BOREN<1:0> R/P-1/1 FOSC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared P = Progra
PIC10(L)F320/322 REGISTER 3-1: CONFIG: CONFIGURATION WORD (CONTINUED) bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits 11 = Brown-out Reset enabled; SBOREN bit is ignored 10 = Brown-out Reset enabled while running, disabled in Sleep; SBOREN bit is ignored 01 = Brown-out Reset controlled by the SBOREN bit in the B
PIC10(L)F320/322 3.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data memory protection are controlled independently. Internal access to the program memory and data memory are unaffected by any code protection setting. 3.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word.
PIC10(L)F320/322 3.5 Device ID and Revision ID The memory location 2006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 9.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.
PIC10(L)F320/322 NOTES: DS41585A-page 26 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 4.0 OSCILLATOR MODULE 4.1 Overview The system can be configured to use an internal calibrated high-frequency oscillator as clock source, with a choice of selectable speeds via software. The oscillator module has a variety of clock sources and selection features that allow it to be used in a range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the oscillator module.
PIC10(L)F320/322 4.2 4.3.2 Clock Source Modes Clock source modes can be classified as external or internal. • Internal clock source (INTOSC) is contained within the oscillator module, which has eight selectable output frequencies, with a maximum internal frequency of 16 MHz. • The External Clock mode (EC) relies on an external signal for the clock source. The system clock can be selected between external or internal clock sources via the FOSC bit of the Configuration Word. 4.
PIC10(L)F320/322 4.3.3 REFERENCE CLOCK OUTPUT CONTROL FOSC/4 output is enabled via the CLKROE bit of CLKRCON register. The signal drives the pin regardless of the TRIS setting.
PIC10(L)F320/322 4.4 Oscillator Control Registers 4.4.1 OSCILLATOR CONTROL The Oscillator Control (OSCCON) register (Register 4-2) displays the oscillator readiness, stability and allows frequency selection of the internal oscillator (INTOSC) system clock.
PIC10(L)F320/322 4.5 External Clock Mode 4.5.1 EC MODE The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the CLKIN input.
PIC10(L)F320/322 NOTES: DS41585A-page 32 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 5.0 RESETS There are multiple ways to reset this device: • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset WDT Reset Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1.
PIC10(L)F320/322 5.1 Power-on Reset (POR) 5.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC10(L)F320/322 FIGURE 5-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
PIC10(L)F320/322 5.3 Low-Power Brown-out Reset (LPBOR) 5.5 The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 5-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 5-2. 5.3.
PIC10(L)F320/322 FIGURE 5-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2011 Microchip Technology Inc.
PIC10(L)F320/322 5.9 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 5-3 and Table 5-4 show the Reset conditions of these registers.
PIC10(L)F320/322 5.10 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) The PCON register bits are shown in Register 5-2.
PIC10(L)F320/322 NOTES: DS41585A-page 40 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 6.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Context Saving during Interrupts Many peripherals produce Interrupts. Refer to the corresponding chapters for details.
PIC10(L)F320/322 6.1 Operation 6.2 Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt events) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1 register) Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins.
PIC10(L)F320/322 FIGURE 6-2: INTERRUPT LATENCY INTOSC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP
PIC10(L)F320/322 FIGURE 6-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 INTOSC CLKR (3) INT pin (1) (1) INTF Interrupt Latency (2) (4) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Forced NOP 0004h 0005h Inst (0004h) Inst (0005h) Forced NOP Inst (0004h) INTF flag is sampled here (every Q1).
PIC10(L)F320/322 6.3 Interrupts During Sleep 6.5 Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC10(L)F320/322 6.6 Interrupt Control Registers Note: 6.6.1 INTCON REGISTER The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 6-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register.
PIC10(L)F320/322 6.6.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 6-2. REGISTER 6-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC10(L)F320/322 6.6.3 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 6-3. REGISTER 6-3: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC10(L)F320/322 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 46 IOCAF — — — — IOCAF3 IOCAF2 IOCAF1 IOCAF0 84 IOCAN — — — — IOCAN3 IOCAN2 IOCAN1 IOCAN0 83 IOCAP — — — — IOCAP3 IOCAP2 IOCAP1 IOCAP0 83 Name INTCON INTEDG T0CS T0SE PSA PIE1 OPTION_REG WPUEN — ADIE — NCO1IE CLC1IE — PS<2:0> TMR2IE — 103 47 PIR1 — ADIF — NC
PIC10(L)F320/322 NOTES: DS41585A-page 50 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 7.0 POWER-DOWN MODE (SLEEP) 7.1 Wake-up from Sleep The Power-down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 7. 8. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled.
PIC10(L)F320/322 7.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared.
PIC10(L)F320/322 8.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC10(L)F320/322 8.1 Independent Clock Source 8.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1ms. See Section 24.0 “Electrical Specifications” for the LFINTOSC tolerances. 8.2 Time-Out Period The WDTPS bits of the WDTCON register set the timeout period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is 2 seconds. 8.
PIC10(L)F320/322 8.
PIC10(L)F320/322 TABLE 8-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 OSCCON — STATUS IRP RP1 — — WDTCON Bit 5 Bit 4 IRCF<2:0> RP0 TO Bit 3 Bit 2 Bit 1 Bit 0 Register on Page HFIOFR — LFIOFR HFIOFS 30 PD Z DC C 15 SWDTEN 55 WDTPS<4:0> Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
PIC10(L)F320/322 9.0 9.1.1 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs).
PIC10(L)F320/322 TABLE 9-1: FLASH MEMORY ORGANIZATION BY DEVICE Device PIC10(L)F320 PIC10(L)F322 9.2.1 Row Erase (words) Write Latches (words) 16 16 FIGURE 9-1: READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register.
PIC10(L)F320/322 FIGURE 9-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PC +3 PC+3 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here PC + 5 INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(
PIC10(L)F320/322 9.2.2 FLASH MEMORY UNLOCK SEQUENCE FIGURE 9-3: The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing.
PIC10(L)F320/322 9.2.3 ERASING FLASH PROGRAM MEMORY FIGURE 9-4: While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 9-2.
PIC10(L)F320/322 EXAMPLE 9-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2.
PIC10(L)F320/322 9.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts.
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES 7 1 0 7 4 3 PMADRL PMADRH - - - - - - - r4 r3 r2 r1 r0 c3 c2 0 7 - c1 c0 5 - 0 7 PMDATH 6 0 PMDATL 8 14 Program Memory Write Latches 4 14 Write Latch #0 00h PMADRL<3:0> Preliminary 14 5 14 14 Write Latch #1 01h 14 Write Latch #14 Write Latch #15 0Eh 0Fh 14 14 14 PMADRH<0>: PMADRL<7:4> CFGS = 0 2011 Microchip Technology Inc.
PIC10(L)F320/322 FIGURE 9-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config.
PIC10(L)F320/322 EXAMPLE 9-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4.
PIC10(L)F320/322 9.3 Modifying Flash Program Memory FIGURE 9-7: When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC10(L)F320/322 9.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Word can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<13> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 9-2.
PIC10(L)F320/322 9.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 9-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM.
PIC10(L)F320/322 9.
PIC10(L)F320/322 REGISTER 9-3: R/W-0/0 PMADRL: PROGRAM MEMORY ADDRESS LOW R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMADR<7:0>: Program Memory Read Address low bits REGISTER 9-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH U-0 U-0 U-0 U-0 U
PIC10(L)F320/322 REGISTER 9-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1(1) R/W-0/0 R/W-0/0 — CFGS LWLO R/W/HC-0/0 R/W/HC-0/q(2) FREE WRERR R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6 CF
PIC10(L)F320/322 REGISTER 9-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, befo
PIC10(L)F320/322 NOTES: DS41585A-page 74 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 10.0 I/O PORT FIGURE 10-1: Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. PORTA has three standard registers for its operation.
PIC10(L)F320/322 10.1 10.1.3 PORTA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 10-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 10-1 shows how to initialize PORTA.
PIC10(L)F320/322 REGISTER 10-1: PORTA: PORTA REGISTER U-0 U-0 U-0 U-0 R-x/x R/W-x/x R/W-x/x R/W-x/x — — — — RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 RA<3:0>: PORTA I/O Value bits (RA3 is read-only) Note 1: Writes to PORTx are actually writt
PIC10(L)F320/322 REGISTER 10-3: LATA: PORTA DATA LATCH REGISTER U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u — — — — — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits Note 1: Writes to PORTx are actually
PIC10(L)F320/322 REGISTER 10-5: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 U-0 U-0 — — — — R/W-1/1 WPUA3 (2) R/W-1/1 R/W-1/1 R/W-1/1 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 WPUA<3:0>: Weak Pull-up PORTA Control bits 1 = Weak Pull-up enabled
PIC10(L)F320/322 TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — — — ANSA2 ANSA1 ANSA0 78 IOCAF — — — — IOCAF3 IOCAF2 IOCAF1 IOCAF0 84 IOCAN — — — — IOCAN3 IOCAN2 IOCAN1 IOCAN0 83 IOCAP — — — — IOCAP3 IOCAP2 IOCAP1 IOCAP0 83 LATA — — — — — LATA2 LATA1 LATA0 78 PORTA — — — — RA3 RA2 RA1 RA0 77 (1) TRISA2 TRISA1 TRISA0 77 WPUA2 WPUA1 WPUA0 79 Name
PIC10(L)F320/322 11.0 INTERRUPT-ON-CHANGE 11.3 The PORTA pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTA pin, or combination of PORTA pins, can be configured to generate an interrupt.
PIC10(L)F320/322 FIGURE 11-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCANx D Q4Q1 Q CK Edge Detect R RAx IOCAPx D Data Bus = 0 or 1 Q Write IOCAFx CK D S Q To Data Bus IOCAFx CK IOCIE R Q2 From all other IOCAFx individual pin detectors Q1 Q2 Q3 Q4 Q4Q1 DS41585A-page 82 Q1 Q1 Q2 Q2 Q3 Q4 Q4Q1 IOC Interrupt to CPU Core Q3 Q4 Q4 Q4Q1 Preliminary Q4Q1 2011 Microchip Technology Inc.
PIC10(L)F320/322 11.6 Interrupt-On-Change Registers REGISTER 11-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’.
PIC10(L)F320/322 REGISTER 11-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — IOCAF3 IOCAF2 IOCAF1 IOCAF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-4 Unimplemented: Read as ‘0’.
PIC10(L)F320/322 12.0 FIXED VOLTAGE REFERENCE (FVR) 12.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC is routed through an independent programmable gain amplifier. The amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels.
PIC10(L)F320/322 12.
PIC10(L)F320/322 13.0 INTERNAL VOLTAGE REGULATOR (IVR) The Internal Voltage Regulator (IVR), which provides operation above 3.6V is available on: • PIC10(L)F320 • PIC10(L)F322 This circuit regulates a voltage for the internal device logic while permitting the VDD and I/O pins to operate at a higher voltage. When VDD approaches the regulated voltage, the IVR output automatically tracks the input voltage. The IVR operates in one of three power modes based on user configuration and peripheral selection.
PIC10(L)F320/322 REGISTER 13-1: U-0 — VREGCON: VOLTAGE REGULATOR CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — bit 7 Legend: R = Readable bit u = Bit is unchanged ‘1’ = Bit is set W = Writable bit x = Bit is unknown ‘0’ = Bit is cleared U-0 — R/W-0/0 VREGPM1 R/W-1/1 Reserved bit 0 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM1: Voltage Regulator Power Mode Selection bit 1 = Power-Save Sleep mode enabled in Sl
PIC10(L)F320/322 14.0 TEMPERATURE INDICATOR MODULE FIGURE 14-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between of -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC10(L)F320/322 TABLE 14-2: SUMMARY OF REGISTERS Name FVRCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FVREN FVRRDY TSEN TSRNG — — ADCON ADRES ADCS<2:0> CHS<2:0> Bit 1 Bit 0 ADFVR<1:0> GO/ DONE ADON A/D Result Register Register on Page 86 96 97 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change. DS41585A-page 90 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 15.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) converts an analog input signal to an 8-bit binary representation of that signal. This device uses three analog input channels, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC10(L)F320/322 15.1 15.1.4 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • Port configuration Channel selection ADC conversion clock source Interrupt control 15.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 10.0 “I/O Port” for more information. Note: 15.1.
PIC10(L)F320/322 TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 125 ns(1) 250 ns(1) 500 ns(1) 2.0 s FOSC/4 100 (1) 250 ns (1) FOSC/8 001 0.5 s(1) FOSC/16 101 1.0 s 4.0 s 1.0 s 2.0 s 8.0 s(2) 1.0 s 2.0 s 4.0 s 16.0 s(2) 010 2.0 s 4.0 s FOSC/64 110 4.0 s FRC x11 1.0-6.0 s(1,3) FOSC/32 Legend: Note 1: 2: 3: 500 ns 8.
PIC10(L)F320/322 15.1.5 INTERRUPTS 15.2 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled.
PIC10(L)F320/322 15.2.5 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC10(L)F320/322 15.3 ADC Register Definitions The following registers are used to control the operation of the ADC.
PIC10(L)F320/322 REGISTER 15-2: R/W-x/u ADRES: ADC RESULT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits 8-bit result 2011 Microchip Technology Inc.
PIC10(L)F320/322 15.4 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 15-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 15-3.
PIC10(L)F320/322 FIGURE 15-3: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.
PIC10(L)F320/322 TABLE 15-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON Bit 6 Bit 5 Bit 4 ADCS<2:0> Bit 3 Bit 2 CHS<2:0> ADRES Bit 1 Bit 0 GO/DONE ADON ADRES<7:0> Register on Page 96 97 ANSELA — — — — — ANSA2 FVRCON FVREN FVRRDY TSEN TSRNG — — INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 46 PIE1 — ADIE — NCO1IE CLC1IE — TMR2IE — 47 PIR1 — ADIF — NCO1IF CLC1IF — TMR2IF — 48 TRISA — — — — — TRISA2 TRISA1 TRISA0 77 Le
PIC10(L)F320/322 16.0 When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. TIMER0 MODULE The Timer0 module is an 8-bit timer/counter with the following features: • • • • • Note: 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow 16.1.
PIC10(L)F320/322 16.1.3 SOFTWARE PROGRAMMABLE PRESCALER 16.1.4 A single software programmable prescaler is available for use with Timer0. The prescaler assignment is controlled by the PSA bit of the OPTION_REG register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. The prescaler is not readable or writable.
PIC10(L)F320/322 REGISTER 16-1: OPTION_REG: OPTION REGISTER R/W-1/u R/W-1/u R/W-1/u R/W-1/u R/W-1/u WPUEN INTEDG T0CS T0SE PSA R/W-1/u R/W-1/u R/W-1/u PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit(1) 1 = Weak pull-ups are disabled 0 = Weak pull-ups are enabled by i
PIC10(L)F320/322 NOTES: DS41585A-page 104 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 17.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: • • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:64) Software programmable postscaler (1:1 to 1:16) Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register.
PIC10(L)F320/322 REGISTER 17-1: U-0 T2CON: TIMER2 CONTROL REGISTER R/W-0/0 R/W-0/0 — R/W-0/0 R/W-0/0 R/W-0/0 TOUTPS<3:0> R/W-0/0 TMR2ON R/W-0/0 T2CKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 1111 = 1:16 Postsc
PIC10(L)F320/322 18.0 Figure 18-1 shows a simplified block diagram of PWM operation. PULSE-WIDTH MODULATION (PWM) MODULE Figure 18-2 shows a typical waveform of the PWM signal.
PIC10(L)F320/322 18.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. Note: 18.1.1 Clearing the PWMxOE bit will relinquish control of the PWMx pin. FUNDAMENTAL OPERATION The PWM module produces a 10-bit resolution output. Timer2 and PR2 set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle.
PIC10(L)F320/322 18.1.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 18-4.
PIC10(L)F320/322 18.1.9 SETUP FOR PWM OPERATION USING PWMx PINS The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. 2. 3. 4. 5. 6. 7. 8. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the PR2 register with the PWM period value. Clear the PWMxDCH register and bits <7:6> of the PWMxDCL register. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register.
PIC10(L)F320/322 18.
PIC10(L)F320/322 REGISTER 18-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWMxDCH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle.
PIC10(L)F320/322 19.0 CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations of software execution. The logic cell selects any combination of the eight input signals and through the use of configurable gates reduces the selected inputs to four logic lines that drive one of eight selectable single-output logic functions.
PIC10(L)F320/322 19.1 19.1.2 CLCx Setup Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four stages are: • • • • Data selection Data gating Logic function selection Output polarity 19.1.1 DATA SELECTION There are eight signals available as inputs to the configurable logic. Four 8-input multiplexers are used to select the inputs to pass on to the next stage.
PIC10(L)F320/322 19.1.3 LOGIC FUNCTION 19.1.5 There are eight available logic functions including: • • • • • • • • The following steps should be followed when setting up the CLCx: AND-OR OR-XOR AND S-R Latch D Flip-Flop with Set and Reset D Flip-Flop with Reset J-K Flip-Flop with Reset Transparent Latch with Set and Reset Logic functions are shown in Figure 19-3. Each logic function has four inputs and one output. The four inputs are the four data gate outputs of the previous stage.
PIC10(L)F320/322 19.2 CLCx Interrupts An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose. TheCLCxIF bit of the associated PIR registers will be set when either edge detector is triggered and its associated enable bit is set. The LCxINTP enables rising edge interrupts and the LCxINTN bit enables falling edge interrupts.
PIC10(L)F320/322 FIGURE 19-2: CLCxIN[0] CLCxIN[1] CLCxIN[2] CLCxIN[3] CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] INPUT DATA SELECTION AND GATING Data Selection 000 Data GATE 1 lcxd1T LCxD1G1T lcxd1N LCxD1G1N 111 LCxD2G1T LCxD1S<2:0> LCxD2G1N CLCxIN[0] CLCxIN[1] CLCxIN[2] CLCxIN[3] CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] LCxD3G1T lcxd2T LCxD3G1N LCxD4G1T 111 LCxD4G1N 000 Data GATE 2 lcxg2 lcxd3T (Same as Data GATE 1) lcxd3N Data GATE 3 111 lcxg3 LCxD3S<2:0> CLCxIN[0] CLCxIN[1] CLCxIN[2] CLCx
PIC10(L)F320/322 FIGURE 19-3: PROGRAMMABLE LOGIC FUNCTIONS AND - OR OR - XOR lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxg3 lcxq lcxg3 lcxg4 lcxg4 LCxMODE<2:0>= 000 LCxMODE<2:0>= 001 4-Input AND S-R Latch lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxg3 S lcxg3 lcxg4 R lcxg4 LCxMODE<2:0>= 010 lcxq Q LCxMODE<2:0>= 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 lcxg2 D S lcxg4 Q lcxq D lcxg2 lcxg1 lcxg1 Q lcxq R R lcxg3 lcxg3 LCxMODE<2:0>= 100 LCxMODE<2:0>= 101 J-K
PIC10(L)F320/322 19.
PIC10(L)F320/322 REGISTER 19-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-x/u U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxPOL: LCOUT Polarity Control bit 1 = The output of the logic cell is inverted 0
PIC10(L)F320/322 REGISTER 19-3: U-0 CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER R/W-x/u — R/W-x/u R/W-x/u LCxD2S<2:0> U-0 — R/W-x/u R/W-x/u R/W-x/u LCxD1S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 LCxD2S<2:0>: Input Data 2 Selection Control bits(1) 111 =
PIC10(L)F320/322 REGISTER 19-4: U-0 CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER R/W-x/u — R/W-x/u R/W-x/u LCxD4S<2:0> U-0 — R/W-x/u R/W-x/u R/W-x/u LCxD3S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 LCxD4S<2:0>: Input Data 4 Selection Control bits(1) 111 =
PIC10(L)F320/322 REGISTER 19-5: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit 1
PIC10(L)F320/322 REGISTER 19-6: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit 1
PIC10(L)F320/322 REGISTER 19-7: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit 1
PIC10(L)F320/322 REGISTER 19-8: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit 1
PIC10(L)F320/322 TABLE 19-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 LC1MODE<2:0> Register on Page CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 119 123 CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 124 CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 125 CLC1GLS3 LC1G4D4
PIC10(L)F320/322 NOTES: DS41585A-page 128 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 20.0 NUMERICALLY CONTROLLED OSCILLATOR (NCO) MODULE The Numerically Controlled Oscillator (NCOx) module is a timer that uses the overflow from the addition of an increment value to divide the input frequency. The advantage of the addition method over simple counter driven timer is that the resolution of division does not vary with the divider value. The NCOx is most useful for applications that requires frequency accuracy and fine resolution at a fixed duty cycle.
NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM Increment 16 (1) Buffer 16 Interrupt event Set NCOxIF flag To CLC and CWG modules NCO1CLK 20 11 LC1OUT FOSC Preliminary HFINTOSC 10 Accumulator 01 20 D To NxOUT bit Q NxOE Overflow Q NCOx Clock NxEN 00 TRIS Control 0 NCOx 1 2 NxCKS<1:0> S Q NxPFM NxPOL R 3 2011 Microchip Technology Inc.
PIC10(L)F320/322 20.1 20.1.3 NCOx OPERATION ADDER The NCOx operates by repeatedly adding a fixed value to an accumulator. Additions occur at the input clock rate. The accumulator will overflow with a carry periodically, which is the raw NCOx output. This effectively reduces the input clock by the ratio of the addition value to the maximum accumulator value. See Equation 20-1. The NCOx Adder is a full adder, which operates asynchronously to the clock source selected.
PIC10(L)F320/322 20.2 FIXED DUTY CYCLE (FDC) MODE In Fixed Duty Cycle (FDC) mode, every time the Accumulator overflows, the output is toggled. This provides a 50% duty cycle, provided that the increment value remains constant. For more information, see Figure 20-2. The FDC mode is selected by clearing the NxPFM bit in the NCOxCON register. 20.3 PULSE FREQUENCY (PF) MODE In Pulse Frequency (PF) mode, every time the Accumulator overflows, the output becomes active for one or more clock periods.
2011 Microchip Technology Inc.
PIC10(L)F320/322 20.5 Interrupts When the Accumulator overflows, the NCOx Interrupt Flag bit, NCOxIF, of the PIR1 register is set. To enable this interrupt event, the following bits must be set: • • • • NxEN bit of the NCOxCON register NCOxIE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt must be cleared by software by clearing the NCOxIF bit in the Interrupt Service Routine. 20.
PIC10(L)F320/322 20.
PIC10(L)F320/322 REGISTER 20-3: R/W-0/0 NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxACC<7:0>: NCOx Accumulator, low byte Note 1: NxPWS applies only when operating in Pulse Frequency mode
PIC10(L)F320/322 REGISTER 20-6: R/W-0/0 NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 NCOxINC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxINC<7:0>: NCOx Increment, low byte REGISTER 20-7: R/W-0/0 NCOxINCH: NCOx INCREMENT REGISTER – HIGH BYTE
PIC10(L)F320/322 TABLE 20-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH NCOx Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLC1SEL0 — LC1D2S2 LC1D2S1 LC1D2S0 — LC1D1S2 LC1D1S1 LC1D1S0 121 CLC1SEL1 — LC1D4S2 LC1D4S1 LC1D4S0 — LC1D3S2 LC1D3S1 LC1D3S0 122 CWG1CON1 G1ASDLB<1:0> INTCON GIE G1ASDLA<1:0> TMR0IE PEIE INTE — — IOCIE TMR0IF G1IS<1:0> INTF IOCIF 150 46 NCO1ACCH NCO1ACCH<15:8> 136 NCO1ACCL NCO1ACCL<7:0> 136 — NCO1ACCU NCO1CLK NCO1CON
PIC10(L)F320/322 21.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band delay from a selection of input sources.
CWG BLOCK DIAGRAM GxASDLA GxCS 00 2 FOSC 2 ‘0’ 10 ‘1’ 11 1 cwg_clock GxASDLA = 01 GxOEA CWGxDBR HFINTOSC 6 1 GxIS 2 Preliminary PWM1OUT PWM2OUT N1OUT LC1OUT EN S Q R Q R = 0 TRISx GxPOLA Input Source CWGxDBF 6 EN GxOEB R TRISx = 0 GxPOLB 1 GxASDLB = 01 00 CWG1FLT (INT pin) 2011 Microchip Technology Inc.
PIC10(L)F320/322 FIGURE 21-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN) cwg_clock PWM1 CWGxA Rising Edge Dead Band Falling Edge Dead Band Rising Edge Dead Band Rising Edge D Falling Edge Dead Band CWGxB 2011 Microchip Technology Inc.
PIC10(L)F320/322 21.1 21.4.2 Fundamental Operation The CWG generates a two output complementary waveform from one of four selectable input sources. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time delay immediately where neither output is driven. This is referred to as dead time and is covered in Section 21.5 “Dead-Band Control”.
PIC10(L)F320/322 21.7 Falling Edge Dead Band The falling edge dead band delays the turn-on of the CWGxB output from when the CWGxA output is turned off. The falling edge dead-band time starts when the falling edge of the input source goes true. When this happens, the CWGxA output is immediately turned off and the falling edge dead-band delay time starts. When the falling edge dead-band delay time is reached, the CWGxB output is turned on.
DEAD-BAND OPERATION, CWGxDBR = 01H, CWGxDBF = 02H cwg_clock Input Source CWGxA CWGxB FIGURE 21-4: DEAD-BAND OPERATION, CWGxDBR = 03H, CWGxDBF = 04H, SOURCE SHORTER THAN DEAD BAND Preliminary cwg_clock Input Source CWGxA source shorter than dead band CWGxB PIC10(L)F320/322 DS41585A-page 144 FIGURE 21-3: 2011 Microchip Technology Inc.
PIC10(L)F320/322 EQUATION 21-1: DEAD-BAND DELAY TIME UNCERTAINTY 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock EXAMPLE 21-1: DEAD-BAND DELAY TIME UNCERTAINTY Fcwg_clock = 16 MHz Therefore: 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock 1 = ------------------16 MHz = 625ns 2011 Microchip Technology Inc.
PIC10(L)F320/322 21.9 Auto-shutdown Control 21.10 Operation During Sleep Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. 21.9.1 SHUTDOWN The Shutdown state can be entered by either of the following two methods: • Software generated • External Input 21.9.1.
PIC10(L)F320/322 21.11 Configuring the CWG 21.11.2.1 The following steps illustrate how to properly configure the CWG to ensure a synchronous start: When the GxARSEN bit of the CWGxCON2 register is cleared, the CWG must be restarted after an auto-shutdown event by software. 1. 2. 3. 4. 5. 6. 7. 8. 9. Ensure that the TRIS control bits corresponding to CWGxA and CWGxB are set so that both are configured as inputs. Clear the GxEN bit, if not already cleared.
SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN = 0) Shutdown Event Ceases PIC10(L)F320/322 DS41585A-page 148 FIGURE 21-5: GxASE Cleared by Software CWG Input Source Shutdown Source GxASE CWG1A Tri-State (No Pulse) CWG1B Tri-State (No Pulse) No Shutdown Preliminary Output Resumes Shutdown FIGURE 21-6: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1) Shutdown Event Ceases GxASE auto-cleared by hardware CWG Input Source Shutdown Source 2011 Microchip Technology Inc.
PIC10(L)F320/322 21.
PIC10(L)F320/322 REGISTER 21-2: R/W-x/u CWGxCON1: CWG CONTROL REGISTER 1 R/W-x/u GxASDLB<1:0> R/W-x/u R/W-x/u GxASDLA<1:0> U-0 — U-0 R/W-0/0 R/W-0/0 GxIS<1:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 GxASDLB<1:0>: CWGx Shutdown State for CWGxB When an auto shutdown
PIC10(L)F320/322 REGISTER 21-3: CWGxCON2: CWG CONTROL REGISTER 2 R/W-0/0 R/W-0/0 GxASE GxARSEN U-0 — U-0 — U-0 — U-0 R/W-0/0 R/W-0/0 — GxASDCLC1 GxASDFLT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 GxASE: Auto-Shutdown Event Status bit 1 = An Auto-Shutdown event has occu
PIC10(L)F320/322 REGISTER 21-4: U-0 CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING DEAD-BAND COUNT REGISTER U-0 — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CWGxDBR<5:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CWGxDB
PIC10(L)F320/322 TABLE 21-1: Name ANSELA CWG1CON0 CWG1CON1 CWG1CON2 CWG1DBF SUMMARY OF REGISTERS ASSOCIATED WITH CWG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — — — ANSA2 ANSA1 ANSA0 78 G1EN G1OEB G1OEA G1POLB — G1CS0 G1ASDLB<1:0> G1POLA — G1ASDLA<1:0> — — — — — G1IS<1:0> 150 151 G1ASE G1ARSEN — — CWG1DBF<5:0> 153 CWG1DBR<5:0> 153 — GxASDCLC1 GxASDFLT 152 CWG1DBR — — LATA — — — — — LATA2 LATA1 LATA0 78 TRISA — — — —
PIC10(L)F320/322 NOTES: DS41585A-page 154 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 22.0 Some programmers produce VPP greater than VIHH (9.0V), an external circuit is required to limit the VPP voltage. See Figure 22-1 for example circuit. IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware.
PIC10(L)F320/322 22.2 FIGURE 22-2: Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC10(L)F320/322 devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. VDD Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2.
PIC10(L)F320/322 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 22-4 for more information.
PIC10(L)F320/322 NOTES: DS41585A-page 158 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 23.0 INSTRUCTION SET SUMMARY The PIC10(L)F320/322 instruction set is highly orthogonal and is comprised of three basic categories: TABLE 23-1: Field Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 23-1, while the various opcode fields are summarized in Table 23-1.
PIC10(L)F320/322 PIC10(L)F320/322 INSTRUCTION SET TABLE 23-2: Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with
PIC10(L)F320/322 23.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: (W) + k (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 127 0b7 Operation: 0 (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
PIC10(L)F320/322 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 f 127 0b<7 Operands: None Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
PIC10(L)F320/322 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC10(L)F320/322 MOVWF Move W to f Syntax: [ label ] MOVF Move f Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 Operation: (W) (f) Operation: (f) (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’. If d = 0, destination is W register. If d = 1, the destination is file register ‘f’ itself.
PIC10(L)F320/322 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: TOS PC, 1 GIE Operation: k (W); TOS PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC10(L)F320/322 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 f 127 d [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC10(L)F320/322 SUBWF Subtract W from f XORWF Exclusive OR W with f Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORWF Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - (W) destination) Operation: (W) .XOR. (f) destination) Status Affected: C, DC, Z Status Affected: Z Description: Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
PIC10(L)F320/322 NOTES: DS41585A-page 168 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 24.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC10F320/322 ........................................................................ -0.
PIC10(L)F320/322 PIC10F320/322 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 24-1: VDD (V) 5.5 2.5 2.3 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 24-1 for each Oscillator mode’s supported frequencies. PIC10LF320/322 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 24-2: 3.6 2.5 1.
PIC10(L)F320/322 24.1 DC Characteristics: PIC10(L)F320/322-I/E (Industrial, Extended) PIC10LF320/322 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC10F320/322 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym. VDD Characteristic VDR Typ† Max. Units PIC10LF320/322 1.8 2.5 — — 3.
PIC10(L)F320/322 FIGURE 24-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: DS41585A-page 172 TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 24.2 DC Characteristics: PIC10(L)F320/322-I/E (Industrial, Extended) PIC10LF320/322 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC10F320/322 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max.
PIC10(L)F320/322 24.2 DC Characteristics: PIC10(L)F320/322-I/E (Industrial, Extended) (Continued) PIC10LF320/322 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC10F320/322 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max.
PIC10(L)F320/322 24.3 DC Characteristics: PIC10(L)F320/322-I/E (Power-Down) PIC10LF320/322 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC10F320/322 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Power-down Base Current D023 D023 D024 D024 Min. Typ† Conditions Max.
PIC10(L)F320/322 24.4 DC Characteristics: PIC10(L)F320/322-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D032 with TTL buffer D032A D033 with Schmitt Trigger buffer D034 MCLR VIH — — 0.8 V 4.5V VDD 5.5V — — 0.15 VDD V 1.8V VDD 4.5V — — 0.2 VDD V 2.
PIC10(L)F320/322 24.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units 8.0 — 9.0 V Conditions Program Memory Programming Specifications D110 VIHH D111 IDDP D112 Voltage on MCLR/VPP pin Supply Current during Programming — — 10 mA VDD for Bulk Erase 2.7 — VDD max. V VDD for Write or Row Erase VDD min. — VDD max. V — 1.
PIC10(L)F320/322 24.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 60 C/W 6-pin SOT-23 package 80 C/W 8-pin PDIP package 8-pin DFN package 90 C/W 31.
PIC10(L)F320/322 24.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC10(L)F320/322 24.8 AC Characteristics: PIC10(L)F320/322-I/E FIGURE 24-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS02 OS03 CLKR (CLKROE = 1) TABLE 24-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions OS01 FOSC External CLKIN Frequency(1) DC — 20 MHz OS02 TOSC External CLKIN Period(1) 31.
PIC10(L)F320/322 FIGURE 24-6: CLKR AND I/O TIMING Cycle Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKR OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 24-3: CLKR AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym.
PIC10(L)F320/322 FIGURE 24-7: RESET, WATCHDOG TIMER, AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 24-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
PIC10(L)F320/322 TABLE 24-4: RESET, WATCHDOG TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions 30 TMCL MCLR Pulse Width (low) 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 31 TWDTLP Low-Power Watchdog Timer Time-out Period 10 16 27 ms VDD = 3.
PIC10(L)F320/322 TABLE 24-6: PIC10(L)F320/322 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 8 AD02 EIL Integral Error — — ±1.7 AD03 EDL Differential Error — — ±1 AD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0V AD05 EGN LSb VREF = 3.
PIC10(L)F320/322 FIGURE 24-10: PIC10(L)F320/322 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON, GO AD134 1 Tcy (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 Tcy ADIF GO Sample DONE Sampling Stopped AD132 Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC10(L)F320/322 NOTES: DS41585A-page 186 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 25.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. 2011 Microchip Technology Inc.
PIC10(L)F320/322 NOTES: DS41585A-page 188 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 26.0 DEVELOPMENT SUPPORT 26.
PIC10(L)F320/322 26.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 26.
PIC10(L)F320/322 26.7 MPLAB SIM Software Simulator 26.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC10(L)F320/322 26.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 26.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC10(L)F320/322 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 6-Lead SOT-23 Example XXNN LA11 8-Lead PDIP (300 mil) Example XXXXXXXX XXXXXNNN 10F320 I/P e3 07Q 1110 YYWW 8-Lead DFN (2x3x0.9 mm) Example BAA 110 20 Legend: XX...
PIC10(L)F320/322 TABLE 27-1: 8-LEAD 2x3 DFN (MC) TOP MARKING Part Number PIC10F322(T)-I/MC TABLE 27-2: Marking 6-LEAD SOT-23 (OT) PACKAGE TOP MARKING Part Number Marking BAA PIC10F322(T)-I/OT PIC10F322(T)-E/MC BAB PIC10F322(T)-E/OT LB PIC10F320(T)-I/MC BAC PIC10F320(T)-I/OT LC PIC10F320(T)-E/MC BAD PIC10F320(T)-E/OT LD PIC10LF322(T)-I/MC BAF PIC10LF322(T)-I/OT LE PIC10LF322(T)-E/MC BAG PIC10LF322(T)-E/OT LF PIC10LF320(T)-I/MC BAH PIC10LF320(T)-I/OT LG PIC10LF320(T)-E/MC BA
PIC10(L)F320/322 27.2 Package Details The following sections give the technical details of the packages.
PIC10(L)F320/322 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41585A-page 196 Preliminary 2011 Microchip Technology Inc.
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PIC10(L)F320/322 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC10(L)F320/322 NOTES: DS41585A-page 200 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 APPENDIX A: DATA SHEET REVISION HISTORY Revision A Original release (7/2011). 2011 Microchip Technology Inc.
PIC10(L)F320/322 NOTES: DS41585A-page 202 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 INDEX A A/D Specifications............................................................ 184 Absolute Maximum Ratings (PIC10(L)F320/322) ............. 169 AC Characteristics Industrial and Extended (PIC10(L)F320/322) ........... 180 Load Conditions ........................................................ 179 ADC .................................................................................... 91 Acquisition Requirements ........................................... 98 Associated registers...
PIC10(L)F320/322 I INDF Register ..................................................................... 17 Indirect Addressing, INDF and FSR registers ..................... 19 Instruction Format ............................................................. 159 Instruction Set ................................................................... 159 ADDLW ..................................................................... 161 ADDWF .....................................................................
PIC10(L)F320/322 PR2 Register....................................................................... 17 Prescaler Shared WDT/Timer0 ................................................. 102 Program Memory ................................................................ 11 Map and Stack (PIC10(L)F320 ................................... 12 Programming, Device Instructions .................................... 159 Pulse Width Modulation (PWM) ........................................
PIC10(L)F320/322 WWW Address.................................................................. 207 WWW, On-Line Support........................................................ 6 DS41585A-page 206 Preliminary 2011 Microchip Technology Inc.
PIC10(L)F320/322 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC10(L)F320/322 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC10(L)F320/322 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
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