Information

 2011-2013 Microchip Technology Inc. DS80000529E-page 3
PIC10(L)F320/322
Silicon Errata Issues
1. Module: Program Flash Memory (PFM)
1.1 Program Flash Memory Writes at Min. VDD
The minimum voltage required for a PFM write
operation is 2.0V for LF parts only.
Work around
None.
Affected Silicon Revisions
2. Module: Complementary Waveform
Generator (CWG)
2.1 CWG Auto-Shutdown Termination
When the Auto-Shutdown Event Status bit,
GxASE, is cleared, the shutdown overrides are
improperly relinquished enabling the CWG outputs
immediately. The proper operation is for the
overrides to remain in effect until the first input
rising edge after the G1ASE bit is cleared.
Work around
None.
Affected Silicon Revisions
3. Module: Numerically Controlled
Oscillator (NCO)
3.1 NCO Output Pin, (NCO1)
The NCO module normally requires that the TRIS
bit associated with the NCO1 output pin is cleared
to enable output, (i.e., TRISA2 = 0). When the
clock reference module output is also enabled,
(CLKROE = 1), then the TRIS bit function will
inadvertently be overridden, configuring the port
pin as an output.
Work around
Disable the Reference Clock Output, (CLKROE =
0), when using the NCO1 output.
Affected Silicon Revisions
4. Module: FVR
4.1 FVR Module
When using the FVR Module, if the gain amplifier
output is set via the ADFVR bit in FVRCON while
the module is disabled (FVREN = 0), the internal
oscillator frequency may shift, the device current
consumption can increase and a Brown-out Reset
may occur. Additionally, after the FVREN is
enabled, a switch from 4x to 1x can also cause a
Reset.
Work around
Set the FVREN bit of FVRCON to enable the
module, prior to adjusting the amplifier output
selection with the ADFVR bit.
Always set the amplifier output selection to off (‘0’)
before disabling the FVR module. When switching
from 4x to 1x, first switch from 4x to 2x and then
from 2x to 1x.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A3).
A1
A2 A3
X
X X
A1 A2 A3
X
X
A1 A2 A3
X
X X
A1
A2 A3
X
X X