Datasheet
Table Of Contents
- Device Included In This Data Sheet:
- High-Performance RISC CPU:
- Special Microcontroller Features:
- Low-Power Features/CMOS Technology:
- Peripheral Features:
- 6-Lead SOT-23 Pin Diagram
- 8-Lead DIP Pin Diagram
- 8-Lead DFN Pin Diagram
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 General Description
- 2.0 Device Varieties
- 3.0 Architectural Overview
- 4.0 Memory Organization
- 5.0 I/O Port
- 5.1 GPIO
- 5.2 TRIS Registers
- 5.3 I/O Interfacing
- FIGURE 5-1: Equivalent Circuit for a Single I/O Pin
- TABLE 5-1: Order of Precedence for Pin Functions
- TABLE 5-2: Requirements to Make Pins Available in Digital Mode
- FIGURE 5-2: Block Diagram of GP0 and GP1
- FIGURE 5-3: Block Diagram of GP2
- FIGURE 5-4: Block Diagram of GP3
- TABLE 5-3: Summary of Port Registers
- 5.4 I/O Programming Considerations
- 6.0 TMR0 Module and TMR0 Register
- 7.0 Analog-to-Digital (A/D) converter
- 8.0 Special Features Of The CPU
- 8.1 Configuration Bits
- 8.2 Oscillator Configurations
- 8.3 Reset
- 8.4 Power-on Reset (POR)
- 8.5 Device Reset Timer (DRT)
- 8.6 Watchdog Timer (WDT)
- 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO/PD/GPWUF/CWUF)
- 8.8 Reset on Brown-out
- 8.9 Power-down Mode (Sleep)
- 8.10 Program Verification/Code Protection
- 8.11 ID Locations
- 8.12 In-Circuit Serial Programming™
- 9.0 Instruction Set Summary
- 10.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 10.1 DC Characteristics: PIC10F220/222 (Industrial)
- 10.2 DC Characteristics: PIC10F220/222 (Extended)
- 10.3 DC Characteristics: PIC10F220/222 (Industrial, Extended)
- 10.4 Timing Parameter Symbology and Load Conditions
- FIGURE 10-2: Load Conditions
- TABLE 10-2: Calibrated Internal RC Frequencies – PIC10F220/222
- FIGURE 10-3: Reset, Watchdog Timer and Device Reset Timer Timing
- TABLE 10-3: Reset, Watchdog Timer and Device Reset Timer – PIC10F220/222
- FIGURE 10-4: Timer0 Clock Timings
- TABLE 10-4: Timer0 Clock Requirements
- TABLE 10-5: A/D Converter Characteristics
- TABLE 10-6: A/D Conversion Requirements
- 11.0 DC and AC Characteristics Graphs and Tables.
- FIGURE 11-1: Idd vs. Vdd Over Fosc (4 MHz)
- FIGURE 11-2: Idd vs. Vdd Over Fosc (8 MHz)
- FIGURE 11-3: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 11-4: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 11-5: Typical WDT Ipd VS. Vdd
- FIGURE 11-6: Maximum WDT Ipd VS. Vdd Over Temperature
- FIGURE 11-7: WDT TIME-OUT VS. Vdd Over Temperature (No Prescaler)
- FIGURE 11-8: Vol VS. Iol Over Temperature (Vdd = 3.0V)
- FIGURE 11-9: Vol VS. Iol Over Temperature (Vdd = 5.0V)
- FIGURE 11-10: Voh VS. Ioh Over Temperature (Vdd = 3.0V)
- FIGURE 11-11: Voh VS. Ioh Over Temperature (Vdd = 5.0V)
- FIGURE 11-12: TTL Input Threshold Vin VS. Vdd
- FIGURE 11-13: Schmitt Trigger Input Threshold Vin VS. Vdd
- 12.0 Development Support
- 12.1 MPLAB Integrated Development Environment Software
- 12.2 MPASM Assembler
- 12.3 MPLAB C18 and MPLAB C30 C Compilers
- 12.4 MPLINK Object Linker/ MPLIB Object Librarian
- 12.5 MPLAB ASM30 Assembler, Linker and Librarian
- 12.6 MPLAB SIM Software Simulator
- 12.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 12.8 MPLAB REAL ICE In-Circuit Emulator System
- 12.9 MPLAB ICD 2 In-Circuit Debugger
- 12.10 MPLAB PM3 Device Programmer
- 12.11 PICSTART Plus Development Programmer
- 12.12 PICkit 2 Development Programmer
- 12.13 Demonstration, Development and Evaluation Boards
- 13.0 Packaging Information
- Appendix A: Revision History
- INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- Product Identification System
PIC10F220/222
DS41270E-page 32 © 2007 Microchip Technology Inc.
7.9 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
HOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 7-1. The source
impedance (R
S) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (V
DD), see Figure 7-1.
The maximum recommended impedance for analog
sources is 10 kΩ. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 7-1 may be used. This equation
assumes that 1/2 LSb error is used (256 steps for the
ADC). The 1/2 LSb error is the maximum error allowed
for the ADC to meet its specified resolution.
EQUATION 7-1: ACQUISITION TIME EXAMPLE
FIGURE 7-1: ANALOG INPUT MODULE
Note 1: The charge holding capacitor (CHOLD) is not discharged after each conversion.
2: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
Assumptions:
Temperature = 50°C and external impedance of 10 k
Ω
5.0V VDD
Tacq = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
=T
AMP + TC + TCOFF
=2
μ
s + TC + [(Temperature - 25°C)(0.05
μ
s/°C)]
Solving for Tc:
Tc = C
HOLD (RIC + RSS + RS) In(1/512)
= -25pF (l k
Ω
+ 7 k
Ω
+ 10 k
Ω
) In(0.00196)
=2.81
μ
s
Therefore:
Tacq = 2
μ
s + 2.81
μ
s + [(50°C-25°C)(0.0 5
μ
s/°C)]
=6.06
μ
s
CPIN
VA
Rs
ANx
5 pF
V
DD
VT = 0.6V
V
T = 0.6V
I
LEAKAGE
RIC ≤ 1k
Sampling
Switch
SS
Rss
C
HOLD = 25 pF
V
SS/VREF-
6V
Sampling Switch
5V
4V
3V
2V
567891011
(kΩ)
V
DD
± 500 nA
RSS
Legend: CPIN = Input Capacitance
V
T = Threshold Voltage
I
LEAKAGE = Leakage current at the pin due
to various junctions
R
IC = Interconnect Resistance
SS = Sampling Switch
C
HOLD = Sample/Hold Capacitance