Datasheet
Table Of Contents
- Device Included In This Data Sheet:
- High-Performance RISC CPU:
- Special Microcontroller Features:
- Low-Power Features/CMOS Technology:
- Peripheral Features:
- 6-Lead SOT-23 Pin Diagram
- 8-Lead DIP Pin Diagram
- 8-Lead DFN Pin Diagram
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 General Description
- 2.0 Device Varieties
- 3.0 Architectural Overview
- 4.0 Memory Organization
- 5.0 I/O Port
- 5.1 GPIO
- 5.2 TRIS Registers
- 5.3 I/O Interfacing
- FIGURE 5-1: Equivalent Circuit for a Single I/O Pin
- TABLE 5-1: Order of Precedence for Pin Functions
- TABLE 5-2: Requirements to Make Pins Available in Digital Mode
- FIGURE 5-2: Block Diagram of GP0 and GP1
- FIGURE 5-3: Block Diagram of GP2
- FIGURE 5-4: Block Diagram of GP3
- TABLE 5-3: Summary of Port Registers
- 5.4 I/O Programming Considerations
- 6.0 TMR0 Module and TMR0 Register
- 7.0 Analog-to-Digital (A/D) converter
- 8.0 Special Features Of The CPU
- 8.1 Configuration Bits
- 8.2 Oscillator Configurations
- 8.3 Reset
- 8.4 Power-on Reset (POR)
- 8.5 Device Reset Timer (DRT)
- 8.6 Watchdog Timer (WDT)
- 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO/PD/GPWUF/CWUF)
- 8.8 Reset on Brown-out
- 8.9 Power-down Mode (Sleep)
- 8.10 Program Verification/Code Protection
- 8.11 ID Locations
- 8.12 In-Circuit Serial Programming™
- 9.0 Instruction Set Summary
- 10.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 10.1 DC Characteristics: PIC10F220/222 (Industrial)
- 10.2 DC Characteristics: PIC10F220/222 (Extended)
- 10.3 DC Characteristics: PIC10F220/222 (Industrial, Extended)
- 10.4 Timing Parameter Symbology and Load Conditions
- FIGURE 10-2: Load Conditions
- TABLE 10-2: Calibrated Internal RC Frequencies – PIC10F220/222
- FIGURE 10-3: Reset, Watchdog Timer and Device Reset Timer Timing
- TABLE 10-3: Reset, Watchdog Timer and Device Reset Timer – PIC10F220/222
- FIGURE 10-4: Timer0 Clock Timings
- TABLE 10-4: Timer0 Clock Requirements
- TABLE 10-5: A/D Converter Characteristics
- TABLE 10-6: A/D Conversion Requirements
- 11.0 DC and AC Characteristics Graphs and Tables.
- FIGURE 11-1: Idd vs. Vdd Over Fosc (4 MHz)
- FIGURE 11-2: Idd vs. Vdd Over Fosc (8 MHz)
- FIGURE 11-3: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 11-4: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 11-5: Typical WDT Ipd VS. Vdd
- FIGURE 11-6: Maximum WDT Ipd VS. Vdd Over Temperature
- FIGURE 11-7: WDT TIME-OUT VS. Vdd Over Temperature (No Prescaler)
- FIGURE 11-8: Vol VS. Iol Over Temperature (Vdd = 3.0V)
- FIGURE 11-9: Vol VS. Iol Over Temperature (Vdd = 5.0V)
- FIGURE 11-10: Voh VS. Ioh Over Temperature (Vdd = 3.0V)
- FIGURE 11-11: Voh VS. Ioh Over Temperature (Vdd = 5.0V)
- FIGURE 11-12: TTL Input Threshold Vin VS. Vdd
- FIGURE 11-13: Schmitt Trigger Input Threshold Vin VS. Vdd
- 12.0 Development Support
- 12.1 MPLAB Integrated Development Environment Software
- 12.2 MPASM Assembler
- 12.3 MPLAB C18 and MPLAB C30 C Compilers
- 12.4 MPLINK Object Linker/ MPLIB Object Librarian
- 12.5 MPLAB ASM30 Assembler, Linker and Librarian
- 12.6 MPLAB SIM Software Simulator
- 12.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 12.8 MPLAB REAL ICE In-Circuit Emulator System
- 12.9 MPLAB ICD 2 In-Circuit Debugger
- 12.10 MPLAB PM3 Device Programmer
- 12.11 PICSTART Plus Development Programmer
- 12.12 PICkit 2 Development Programmer
- 12.13 Demonstration, Development and Evaluation Boards
- 13.0 Packaging Information
- Appendix A: Revision History
- INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- Product Identification System

© 2007 Microchip Technology Inc. DS41270E-page 17
PIC10F220/222
4.5 OPTION Register
The OPTION register is a 8-bit wide, write-only register,
which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
The OPTION register is not memory mapped and is
therefore only addressable by executing the OPTION
instruction, the contents of the W register will be trans-
ferred to the OPTION register. A Reset sets the
OPTION<7:0> bits.
Note: If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are disabled
for that pin (i.e., note that TRIS overrides
Option control of GPPU
and GPWU).
Note: If the T0CS bit is set to ‘1’, it will override
the TRIS function on the T0CKI pin.
REGISTER 4-2: OPTION REGISTER
W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1
GPWU
GPPU T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GPWU
: Enable Wake-up On Pin Change bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 6 GPPU
: Enable Weak Pull-ups bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin)
0 = Transition on internal instruction cycle clock, F
OSC/4
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on the T0CKI pin
0 = Increment on low-to-high transition on the T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0 PS<2:0>: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value Timer0 Rate WDT Rate