Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOT 23 6 8-Bit 8 MHz I/O number 4

Table Of Contents

Device Included In This Data Sheet:
High-Performance RISC CPU:
Special Microcontroller Features:
Low-Power Features/CMOS Technology:
Peripheral Features:
6-Lead SOT-23 Pin Diagram
8-Lead DIP Pin Diagram
8-Lead DFN Pin Diagram
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 General Description
- 1.1 Applications
  - TABLE 1-1: PIC10F220/222 Devices(1), (2)
2.0 Device Varieties
- 2.1 Quick Turn Programming (QTP) Devices
- 2.2 Serialized Quick Turn ProgrammingSM (SQTPSM) Devices
3.0 Architectural Overview
- FIGURE 3-1: Block Diagram
- TABLE 3-1: Pinout Description
- 3.1 Clocking Scheme/Instruction Cycle
- 3.2 Instruction Flow/Pipelining
  - FIGURE 3-2: Clock/Instruction Cycle
  - EXAMPLE 3-1: Instruction Pipeline Flow
4.0 Memory Organization
- 4.1 Program Memory Organization for the PIC10F220
  - FIGURE 4-1: Program Memory Map and Stack for the PIC10F220
- 4.2 Program Memory Organization for the PIC10F222
  - FIGURE 4-2: Program Memory Map and Stack for the PIC10F222
- 4.3 Data Memory Organization
  - 4.3.1 General Purpose Register File
    - FIGURE 4-3: PIC10F220 Register File Map
    - FIGURE 4-4: PIC10F222 Register File Map
  - 4.3.2 Special Function Registers
    - TABLE 4-1: Special Function Register (SFR) Summary
- 4.4 STATUS Register
  - Register 4-1: Status Register (Address: 03h)
- 4.5 OPTION Register
  - Register 4-2: Option Register
- 4.6 OSCCAL Register
  - Register 4-3: OSCCAL – Oscillator Calibration Register (Address: 05h)
- 4.7 Program Counter
  - FIGURE 4-5: Loading of PC Branch Instructions
  - 4.7.1 Effects Of Reset
- 4.8 Stack
- 4.9 Indirect Data Addressing; INDF and FSR Registers
  - 4.9.1 Indirect Addressing
    - EXAMPLE 4-1: How to Clear RAM Using Indirect Addressing
    - FIGURE 4-6: Direct/Indirect Addressing
5.0 I/O Port
- 5.1 GPIO
- 5.2 TRIS Registers
- 5.3 I/O Interfacing
- 5.4 I/O Programming Considerations
  - 5.4.1 Bidirectional I/O Ports
    - EXAMPLE 5-1: I/O Port Read-modify- write Instructions
  - 5.4.2 Successive Operations on I/O Ports
    - FIGURE 5-5: Successive I/O Operation
6.0 TMR0 Module and TMR0 Register
- FIGURE 6-1: TIMER0 Block Diagram
- FIGURE 6-2: TIMER0 Timing: Internal Clock/No Prescale
- FIGURE 6-3: TIMER0 Timing: Internal Clock/Prescale 1:2
- TABLE 6-1: Registers Associated With TIMER0
- 6.1 Using Timer0 With An External Clock
  - 6.1.1 External Clock Synchronization
  - 6.1.2 TIMER0 Increment Delay
    - FIGURE 6-4: TIMER0 Timing with External Clock
- 6.2 Prescaler
  - 6.2.1 Switching Prescaler Assignment
7.0 Analog-to-Digital (A/D) converter
- 7.1 Clock Divisors
- 7.2 Voltage Reference
- 7.3 Analog Mode Selection
- 7.4 A/D Converter Channel Selection
- 7.5 The GO/DONE bit
- 7.6 Sleep
  - TABLE 7-1: Effects of Sleep and Wake on ADCON0
- 7.7 Analog Conversion Result Register
- 7.8 Internal Absolute Voltage Reference
  - Register 7-1: ADCON0: A/D Converter 0 Register
  - Register 7-2: Adres: Analog Conversion Result Register
- 7.9 A/D Acquisition Requirements
  - EQUATION 7-1: Acquisition Time Example
  - FIGURE 7-1: aNALOG iNPUT mODULE
8.0 Special Features Of The CPU
- 8.1 Configuration Bits
  - Register 8-1: CONFIG: Configuration Word(1)
- 8.2 Oscillator Configurations
  - 8.2.1 Oscillator Types
  - 8.2.2 Internal 4/8 MHz Oscillator
- 8.3 Reset
- 8.4 Power-on Reset (POR)
- 8.5 Device Reset Timer (DRT)
  - TABLE 8-3: DRT (Device Reset Timer Period)
- 8.6 Watchdog Timer (WDT)
  - 8.6.1 WDT Period
  - 8.6.2 WDT Programming Considerations
    - FIGURE 8-6: Watchdog Timer Block Diagram
    - TABLE 8-4: Summary of Registers Associated with the Watchdog Timer
- 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO/PD/GPWUF/CWUF)
  - TABLE 8-5: TO/PD/GPWUF Status After Reset
- 8.8 Reset on Brown-out
- 8.9 Power-down Mode (Sleep)
  - 8.9.1 Sleep
  - 8.9.2 Wake-up from Sleep
- 8.10 Program Verification/Code Protection
- 8.11 ID Locations
- 8.12 In-Circuit Serial Programming™
  - FIGURE 8-10: Typical In-Circuit Serial Programming™ Connection
9.0 Instruction Set Summary
- TABLE 9-1: Opcode Field Descriptions
- FIGURE 9-1: General Format for Instructions
- TABLE 9-2: Instruction Set Summary
- 9.1 Instruction Description
10.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
  - FIGURE 10-1: Voltage-Frequency Graph, -40°C £ ta £ +125°C
- 10.1 DC Characteristics: PIC10F220/222 (Industrial)
- 10.2 DC Characteristics: PIC10F220/222 (Extended)
- 10.3 DC Characteristics: PIC10F220/222 (Industrial, Extended)
  - TABLE 10-1: Pull-up Resistor Ranges
- 10.4 Timing Parameter Symbology and Load Conditions
11.0 DC and AC Characteristics Graphs and Tables.
- FIGURE 11-1: Idd vs. Vdd Over Fosc (4 MHz)
- FIGURE 11-2: Idd vs. Vdd Over Fosc (8 MHz)
- FIGURE 11-3: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 11-4: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 11-5: Typical WDT Ipd VS. Vdd
- FIGURE 11-6: Maximum WDT Ipd VS. Vdd Over Temperature
- FIGURE 11-7: WDT TIME-OUT VS. Vdd Over Temperature (No Prescaler)
- FIGURE 11-8: Vol VS. Iol Over Temperature (Vdd = 3.0V)
- FIGURE 11-9: Vol VS. Iol Over Temperature (Vdd = 5.0V)
- FIGURE 11-10: Voh VS. Ioh Over Temperature (Vdd = 3.0V)
- FIGURE 11-11: Voh VS. Ioh Over Temperature (Vdd = 5.0V)
- FIGURE 11-12: TTL Input Threshold Vin VS. Vdd
- FIGURE 11-13: Schmitt Trigger Input Threshold Vin VS. Vdd
12.0 Development Support
- 12.1 MPLAB Integrated Development Environment Software
- 12.2 MPASM Assembler
- 12.3 MPLAB C18 and MPLAB C30 C Compilers
- 12.4 MPLINK Object Linker/ MPLIB Object Librarian
- 12.5 MPLAB ASM30 Assembler, Linker and Librarian
- 12.6 MPLAB SIM Software Simulator
- 12.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 12.8 MPLAB REAL ICE In-Circuit Emulator System
- 12.9 MPLAB ICD 2 In-Circuit Debugger
- 12.10 MPLAB PM3 Device Programmer
- 12.11 PICSTART Plus Development Programmer
- 12.12 PICkit 2 Development Programmer
- 12.13 Demonstration, Development and Evaluation Boards
13.0 Packaging Information
- 13.1 Package Marking Information
  - TABLE 13-1: 8-Lead 2X3 dfn (mc) tOP mARKINg
  - TABLE 13-2: 6-Lead SOT-23 (OT) Package tOP mARKINg
Appendix A: Revision History
- Revision A
- Revision B (03/2006)
- Revision C (08/2006)
- Revision D (02/2007)
- Revision E (06/2007)
INDEX
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PIC10F220/222

TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY

4.4 STATUS Register

This register contains the arithmetic status of the ALU,

the Reset status and the page preselect bit.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO

and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu (where u = unchanged).

Therefore, it is recommended that only BCF, BSF and

MOVWF instructions be used to alter the STATUS regis-

ter. These instructions do not affect the Z, DC or C bits

from the STATUS register. For other instructions, which

do affect Status bits, see Instruction Set Summary.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

(2)

Page #

00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20

01h TMR0 8-Bit Real-Time Clock/Counter xxxx xxxx 25

02h PCL

(1)

Low Order 8 Bits of PC 1111 1111 19

03h STATUS GPWUF

— —TOPD ZDCC0--1 1xxx

(3)

04h FSR Indirect Data Memory Address Pointer 111x xxxx 20

05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4 1111 1110 18

06h GPIO

— — — — GP3 GP2 GP1 GP0 ---- xxxx 21

07h

ADCON0

ANS1 ANS0

— — CHS1 CHS0 GO/DONE ADON 11-- 1100 30

08h ADRES Result of Analog-to-Digital Conversion xxxx xxxx 31

N/A TRISGPIO

— — — — I/O Control Register ---- 1111 23

N/A

OPTION

GPWU

GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 17

Legend: – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter” for an

explanation of how to access these bits.

2: Other (non Power-up) Resets include external Reset through MCLR

, Watchdog Timer and wake-up on pin change

Reset.

3: See Table 8-1 for other Reset specific values.