Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOT 23 6 8-Bit 8 MHz I/O number 4

Table Of Contents

Device Included In This Data Sheet:
High-Performance RISC CPU:
Special Microcontroller Features:
Low-Power Features/CMOS Technology:
Peripheral Features:
6-Lead SOT-23 Pin Diagram
8-Lead DIP Pin Diagram
8-Lead DFN Pin Diagram
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 General Description
- 1.1 Applications
  - TABLE 1-1: PIC10F220/222 Devices(1), (2)
2.0 Device Varieties
- 2.1 Quick Turn Programming (QTP) Devices
- 2.2 Serialized Quick Turn ProgrammingSM (SQTPSM) Devices
3.0 Architectural Overview
- FIGURE 3-1: Block Diagram
- TABLE 3-1: Pinout Description
- 3.1 Clocking Scheme/Instruction Cycle
- 3.2 Instruction Flow/Pipelining
  - FIGURE 3-2: Clock/Instruction Cycle
  - EXAMPLE 3-1: Instruction Pipeline Flow
4.0 Memory Organization
- 4.1 Program Memory Organization for the PIC10F220
  - FIGURE 4-1: Program Memory Map and Stack for the PIC10F220
- 4.2 Program Memory Organization for the PIC10F222
  - FIGURE 4-2: Program Memory Map and Stack for the PIC10F222
- 4.3 Data Memory Organization
  - 4.3.1 General Purpose Register File
    - FIGURE 4-3: PIC10F220 Register File Map
    - FIGURE 4-4: PIC10F222 Register File Map
  - 4.3.2 Special Function Registers
    - TABLE 4-1: Special Function Register (SFR) Summary
- 4.4 STATUS Register
  - Register 4-1: Status Register (Address: 03h)
- 4.5 OPTION Register
  - Register 4-2: Option Register
- 4.6 OSCCAL Register
  - Register 4-3: OSCCAL – Oscillator Calibration Register (Address: 05h)
- 4.7 Program Counter
  - FIGURE 4-5: Loading of PC Branch Instructions
  - 4.7.1 Effects Of Reset
- 4.8 Stack
- 4.9 Indirect Data Addressing; INDF and FSR Registers
  - 4.9.1 Indirect Addressing
    - EXAMPLE 4-1: How to Clear RAM Using Indirect Addressing
    - FIGURE 4-6: Direct/Indirect Addressing
5.0 I/O Port
- 5.1 GPIO
- 5.2 TRIS Registers
- 5.3 I/O Interfacing
- 5.4 I/O Programming Considerations
  - 5.4.1 Bidirectional I/O Ports
    - EXAMPLE 5-1: I/O Port Read-modify- write Instructions
  - 5.4.2 Successive Operations on I/O Ports
    - FIGURE 5-5: Successive I/O Operation
6.0 TMR0 Module and TMR0 Register
- FIGURE 6-1: TIMER0 Block Diagram
- FIGURE 6-2: TIMER0 Timing: Internal Clock/No Prescale
- FIGURE 6-3: TIMER0 Timing: Internal Clock/Prescale 1:2
- TABLE 6-1: Registers Associated With TIMER0
- 6.1 Using Timer0 With An External Clock
  - 6.1.1 External Clock Synchronization
  - 6.1.2 TIMER0 Increment Delay
    - FIGURE 6-4: TIMER0 Timing with External Clock
- 6.2 Prescaler
  - 6.2.1 Switching Prescaler Assignment
7.0 Analog-to-Digital (A/D) converter
- 7.1 Clock Divisors
- 7.2 Voltage Reference
- 7.3 Analog Mode Selection
- 7.4 A/D Converter Channel Selection
- 7.5 The GO/DONE bit
- 7.6 Sleep
  - TABLE 7-1: Effects of Sleep and Wake on ADCON0
- 7.7 Analog Conversion Result Register
- 7.8 Internal Absolute Voltage Reference
  - Register 7-1: ADCON0: A/D Converter 0 Register
  - Register 7-2: Adres: Analog Conversion Result Register
- 7.9 A/D Acquisition Requirements
  - EQUATION 7-1: Acquisition Time Example
  - FIGURE 7-1: aNALOG iNPUT mODULE
8.0 Special Features Of The CPU
- 8.1 Configuration Bits
  - Register 8-1: CONFIG: Configuration Word(1)
- 8.2 Oscillator Configurations
  - 8.2.1 Oscillator Types
  - 8.2.2 Internal 4/8 MHz Oscillator
- 8.3 Reset
- 8.4 Power-on Reset (POR)
- 8.5 Device Reset Timer (DRT)
  - TABLE 8-3: DRT (Device Reset Timer Period)
- 8.6 Watchdog Timer (WDT)
  - 8.6.1 WDT Period
  - 8.6.2 WDT Programming Considerations
    - FIGURE 8-6: Watchdog Timer Block Diagram
    - TABLE 8-4: Summary of Registers Associated with the Watchdog Timer
- 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO/PD/GPWUF/CWUF)
  - TABLE 8-5: TO/PD/GPWUF Status After Reset
- 8.8 Reset on Brown-out
- 8.9 Power-down Mode (Sleep)
  - 8.9.1 Sleep
  - 8.9.2 Wake-up from Sleep
- 8.10 Program Verification/Code Protection
- 8.11 ID Locations
- 8.12 In-Circuit Serial Programming™
  - FIGURE 8-10: Typical In-Circuit Serial Programming™ Connection
9.0 Instruction Set Summary
- TABLE 9-1: Opcode Field Descriptions
- FIGURE 9-1: General Format for Instructions
- TABLE 9-2: Instruction Set Summary
- 9.1 Instruction Description
10.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
  - FIGURE 10-1: Voltage-Frequency Graph, -40°C £ ta £ +125°C
- 10.1 DC Characteristics: PIC10F220/222 (Industrial)
- 10.2 DC Characteristics: PIC10F220/222 (Extended)
- 10.3 DC Characteristics: PIC10F220/222 (Industrial, Extended)
  - TABLE 10-1: Pull-up Resistor Ranges
- 10.4 Timing Parameter Symbology and Load Conditions
11.0 DC and AC Characteristics Graphs and Tables.
- FIGURE 11-1: Idd vs. Vdd Over Fosc (4 MHz)
- FIGURE 11-2: Idd vs. Vdd Over Fosc (8 MHz)
- FIGURE 11-3: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 11-4: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 11-5: Typical WDT Ipd VS. Vdd
- FIGURE 11-6: Maximum WDT Ipd VS. Vdd Over Temperature
- FIGURE 11-7: WDT TIME-OUT VS. Vdd Over Temperature (No Prescaler)
- FIGURE 11-8: Vol VS. Iol Over Temperature (Vdd = 3.0V)
- FIGURE 11-9: Vol VS. Iol Over Temperature (Vdd = 5.0V)
- FIGURE 11-10: Voh VS. Ioh Over Temperature (Vdd = 3.0V)
- FIGURE 11-11: Voh VS. Ioh Over Temperature (Vdd = 5.0V)
- FIGURE 11-12: TTL Input Threshold Vin VS. Vdd
- FIGURE 11-13: Schmitt Trigger Input Threshold Vin VS. Vdd
12.0 Development Support
- 12.1 MPLAB Integrated Development Environment Software
- 12.2 MPASM Assembler
- 12.3 MPLAB C18 and MPLAB C30 C Compilers
- 12.4 MPLINK Object Linker/ MPLIB Object Librarian
- 12.5 MPLAB ASM30 Assembler, Linker and Librarian
- 12.6 MPLAB SIM Software Simulator
- 12.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 12.8 MPLAB REAL ICE In-Circuit Emulator System
- 12.9 MPLAB ICD 2 In-Circuit Debugger
- 12.10 MPLAB PM3 Device Programmer
- 12.11 PICSTART Plus Development Programmer
- 12.12 PICkit 2 Development Programmer
- 12.13 Demonstration, Development and Evaluation Boards
13.0 Packaging Information
- 13.1 Package Marking Information
  - TABLE 13-1: 8-Lead 2X3 dfn (mc) tOP mARKINg
  - TABLE 13-2: 6-Lead SOT-23 (OT) Package tOP mARKINg
Appendix A: Revision History
- Revision A
- Revision B (03/2006)
- Revision C (08/2006)
- Revision D (02/2007)
- Revision E (06/2007)
INDEX
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PIC10F220/222

4.3 Data Memory Organization

Data memory is composed of registers or bytes of

RAM. Therefore, data memory for a device is specified

by its register file. The register file is divided into two

functional groups: Special Function Registers (SFR)

and General Purpose Registers (GPR).

The Special Function Registers include the TMR0 reg-

ister, the Program Counter (PCL), the STATUS register,

the I/O register (GPIO) and the File Select Register

(FSR). In addition, Special Function Registers are used

to control the I/O port configuration and prescaler

options.

The General Purpose Registers are used for data and

control information under command of the instructions.

For the PIC10F220, the register file is composed of 9

Special Function Registers and 16 General Purpose

Registers (Figure 4-3, Figure 4-4).

For the PIC10F222, the register file is composed of 9

Special Function Registers and 23 General Purpose

Registers (Figure 4-4).

4.3.1 GENERAL PURPOSE REGISTER

FILE

The General Purpose Register file is accessed, either

directly or indirectly, through the File Select Register

(FSR). See Section 4.9 “Indirect Data Addressing;

INDF and FSR Registers”.

FIGURE 4-3: PIC10F220 REGISTER

FILE MAP

FIGURE 4-4: PIC10F222 REGISTER

FILE MAP

4.3.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the

operation of the device (Table 4-1).

The Special Function Registers can be classified into

two sets. The Special Function Registers associated

with the “core” functions are described in this section.

Those related to the operation of the peripheral

features are described in the section for each

peripheral feature.

File Address

00h

01h

02h

03h

04h

05h

06h

07h

10h

INDF

(1)

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

General

Purpose

Registers

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing; INDF and

FSR Registers”.

2: Unimplemented, read as 00h.

08h

ADCON0

0Fh

1Fh

Unimplemented

(2)

ADRES

09h