PIC10F220/222 Data Sheet High-Performance Microcontrollers with 8-bit A/D © 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC10F220/222 6-Pin, 8-Bit Flash Microcontrollers Device Included In This Data Sheet: Low-Power Features/CMOS Technology: • PIC10F220 • PIC10F222 • Operating Current: - < 175 μA @ 2V, 4 MHz • Standby Current: - 100 nA @ 2V, typical • Low-Power, High-Speed Flash Technology: - 100,000 Flash endurance - > 40-year retention • Fully Static Design • Wide Operating Voltage Range: 2.0V to 5.
PIC10F220/222 1 VSS 2 GP1/AN1/ICSPCLK 3 PIC10F220/222 GP0/AN0/ICSPDAT 6 GP3/MCLR/VPP 5 VDD 4 GP2/T0CKI/FOSC4 PIC10F220/222 6-Lead SOT-23 Pin Diagram 8 GP3/MCLR/VPP 7 VSS 6 N/C 5 GP0/AN0/ICSPDAT 8 GP3/MCLR/VPP 7 VSS 6 N/C 5 GP0/AN0/ICSPDAT 8-Lead DIP Pin Diagram N/C 1 VDD 2 GP2/T0CKI/FOSC4 3 GP1/AN1/ICSPCLK 4 DS41270E-page 2 N/C 1 VDD 2 GP2/T0CKI/FOSC4 3 GP1/AN1/ICSPCLK 4 PIC10F220/222 8-Lead DFN Pin Diagram © 2007 Microchip Technology Inc.
PIC10F220/222 Table of Contents 1.0 General Description...................................................................................................................................................................... 5 2.0 Device Varieties .......................................................................................................................................................................... 7 3.0 Architectural Overview ...................................................................
PIC10F220/222 NOTES: DS41270E-page 4 © 2007 Microchip Technology Inc.
PIC10F220/222 1.0 GENERAL DESCRIPTION The PIC10F220/222 devices from Microchip Technology are low-cost, high-performance, 8-bit, fullystatic Flash-based CMOS microcontrollers. They employ a RISC architecture with only 33 single-word/ single-cycle instructions. All instructions are singlecycle (1 μs) except for program branches, which take two cycles. The PIC10F220/222 devices deliver performance in an order of magnitude higher than their competitors in the same price category.
PIC10F220/222 NOTES: DS41270E-page 6 © 2007 Microchip Technology Inc.
PIC10F220/222 2.0 DEVICE VARIETIES A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC10F220/222 Product Identification System at the back of this data sheet to specify the correct part number. 2.1 Quick Turn Programming (QTP) Devices Microchip offers a QTP programming service for factory production orders.
PIC10F220/222 NOTES: DS41270E-page 8 © 2007 Microchip Technology Inc.
PIC10F220/222 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC10F220/222 devices can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC10F220/222 devices use a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus.
PIC10F220/222 FIGURE 3-1: BLOCK DIAGRAM 9-10 512 x 12 or 256 x 12 GPIO GP0/AN0/ICSPDAT GP1/AN1/ICSPCLK GP2/T0CKI/FOSC4 GP3/MCLR/VPP RAM Program Memory 23 or 16 bytes STACK1 STACK2 Program Bus 8 Data Bus Program Counter Flash File Registers 12 RAM Addr 9 Addr MUX Instruction Reg Direct Addr 5 5-7 Indirect Addr FSR Reg STATUS Reg 8 3 MUX Device Reset Timer Instruction Decode & Control Power-on Reset Timing Generation Watchdog Timer Internal RC Clock ALU AN0 8 ADC W Reg AN1 Timer
PIC10F220/222 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g.
PIC10F220/222 NOTES: DS41270E-page 12 © 2007 Microchip Technology Inc.
PIC10F220/222 MEMORY ORGANIZATION The PIC10F220/222 memories are organized into program memory and data memory. Data memory banks are accessed using the File Select Register (FSR). 4.1 Program Memory Organization for the PIC10F220 The PIC10F220 devices have a 9-bit Program Counter (PC) capable of addressing a 512 x 12 program memory space. Only the first 256 x 12 (0000h-00FFh) for the PIC10F220 are physically implemented (see Figure 4-1).
PIC10F220/222 4.3 Data Memory Organization FIGURE 4-4: Data memory is composed of registers or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR).
PIC10F220/222 TABLE 4-1: Address SPECIAL FUNCTION REGISTER (SFR) SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset(2) Page # 20 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 01h TMR0 8-Bit Real-Time Clock/Counter xxxx xxxx 25 02h PCL(1) Low Order 8 Bits of PC 1111 1111 19 03h STATUS GPWUF 0--1 1xxx(3) 15 04h FSR Indirect Data Memory Address Pointer 111x xxxx 20 05h OSCCAL 1111 1110 18 06h
PIC10F220/222 REGISTER 4-1: STATUS REGISTER (ADDRESS: 03h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x GPWUF — — TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPWUF: GPIO Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset bit 6 Reserved: Do not use.
PIC10F220/222 4.5 OPTION Register The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0. The OPTION register is not memory mapped and is therefore only addressable by executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION<7:0> bits.
PIC10F220/222 4.6 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal precision 4/8 MHz oscillator. It contains seven bits for calibration. Note: Erasing the device will also erase the preprogrammed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. After you move in the calibration constant, do not change the value. See Section 8.2.
PIC10F220/222 4.7 4.7.1 Program Counter As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0>.
PIC10F220/222 4.9 EXAMPLE 4-1: Indirect Data Addressing; INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. 4.9.
PIC10F220/222 5.0 I/O PORT The TRIS registers are “write-only” and are set (output drivers disabled) upon Reset. As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g., MOVF GPIO, W) always read the I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance) since the I/O control registers are all set. 5.1 5.
PIC10F220/222 FIGURE 5-2: BLOCK DIAGRAM OF GP0 AND GP1 FIGURE 5-3: I/O Pin(1) Data Bus D GPPU D Q WR Port CK W Reg I/O Pin FOSC4 OSCCAL<0> D Q TRIS Latch (1) TRIS ‘f’ Q Q CK W Reg Data Latch Q Data Latch WR Port Data Bus BLOCK DIAGRAM OF GP2 Q CK Reset D Q T0CS TRIS Latch TRIS ‘f’ CK Q RD Port Reset T0CKI Analog Enable Note 1: I/O pins have protection diodes to VDD and VSS.
PIC10F220/222 TABLE 5-3: Address N/A SUMMARY OF PORT REGISTERS Name TRISGPIO Bit 7 Bit 6 Bit 5 Bit 4 — — — — Bit 3 Bit 2 Bit 1 Bit 0 I/O Control Registers Value on Power-On Reset Value on All Other Resets ---- 1111 ---- 1111 N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 03h STATUS GPWUF — — TO PD Z DC C 0001 1xxx q00q quuu(1) — — — — GP3 GP2 GP1 GP0 ---- xxxx ---- uuuu 06h GPIO Legend: Shaded cells not used by PORT registers, read
PIC10F220/222 NOTES: DS41270E-page 24 © 2007 Microchip Technology Inc.
PIC10F220/222 6.0 TMR0 MODULE AND TMR0 REGISTER Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1 “Using Timer0 With An External Clock”.
PIC10F220/222 FIGURE 6-3: PC (Program Counter) TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 Instruction Fetch PC MOVWF TMR0 T0 Timer0 PC + 2 PC + 4 PC + 5 NT0 Write TMR0 executed TABLE 6-1: PC + 3 T0 + 1 Instruction Executed Address PC + 1 Read TMR0 reads NT0 NT0 + 1 Read TMR0 reads NT0 Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2 Read TMR0 reads NT0 REGISTERS ASSOCIATED WITH TIMER0 N
PIC10F220/222 6.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-4 shows the delay from the external clock edge to the timer incrementing.
PIC10F220/222 6.2.1 SWITCHING PRESCALER ASSIGNMENT To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution).
PIC10F220/222 7.0 ANALOG-TO-DIGITAL (A/D) CONVERTER Note: The A/D Converter module consumes power when the ADON bit is set even when no channels are selected as analog inputs. For low-power applications, it is recommended that the ADON bit be cleared when the A/D Converter is not in use. The A/D converter allows conversion of an analog signal into an 8-bit digital signal. 7.1 Clock Divisors The A/D Converter has a single clock source setting, INTOSC/4.
PIC10F220/222 7.7 Analog Conversion Result Register 7.8 The ADRES register contains the results of the last conversion. These results are present during the sampling period of the next analog conversion process. After the sampling period is over, ADRES is cleared (= 0). A ‘leading one’ is then right shifted into the ADRES to serve as an internal conversion complete bit. As each bit weight, starting with the MSb, is converted, the leading one is shifted right and the converted bit is stuffed into ADRES.
PIC10F220/222 REGISTER 7-2: ADRES: ANALOG CONVERSION RESULT REGISTER R-X R-X R-X R-X R-X R-X R-X R-X ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<7:0> © 2007 Microchip Technology Inc.
PIC10F220/222 7.9 A/D Acquisition Requirements After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 7-1 may be used. This equation assumes that 1/2 LSb error is used (256 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.
PIC10F220/222 8.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits that deal with the needs of realtime applications. The PIC10F220/222 microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving operating modes and offer code protection.
PIC10F220/222 8.2 Oscillator Configurations 8.2.1 OSCILLATOR TYPES The PIC10F220/222 devices are offered with internal oscillator mode only. • INTOSC: Internal 4/8 MHz Oscillator 8.2.2 INTERNAL 4/8 MHz OSCILLATOR The internal oscillator provides a 4/8 MHz (nominal) system clock (see Section 10.0 “Electrical Characteristics” for information on variation over voltage and temperature).
PIC10F220/222 TABLE 8-2: RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr: 03h PCL Addr: 02h Power-on Reset 0--1 1xxx 1111 1111 MCLR Reset during normal operation 0--u uuuu 1111 1111 MCLR Reset during Sleep 0--1 0uuu 1111 1111 WDT Reset during Sleep 0--0 0uuu 1111 1111 WDT Reset normal operation 0--0 uuuu 1111 1111 Wake-up from Sleep on pin change 1--1 0uuu 1111 1111 Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’. 8.3.
PIC10F220/222 FIGURE 8-2: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) GP3/MCLR/VPP MCLR Reset MCLRE WDT Reset WDT Time-out Pin Change Sleep S Q R Q Start-up Timer 1.
PIC10F220/222 FIGURE 8-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min. © 2007 Microchip Technology Inc.
PIC10F220/222 8.5 Device Reset Timer (DRT) On the PIC10F220/222 devices, the DRT runs any time the device is powered up. The DRT operates on an internal oscillator. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the oscillator to stabilize. The on-chip DRT keeps the devices in a Reset condition for approximately 1.125 ms after MCLR has reached a logic high (VIH MCLR) level.
PIC10F220/222 FIGURE 8-6: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure 6-5) 0 M U X 1 Watchdog Timer Postscaler 3 8-to-1 MUX PS<2:0> PSA WDT Enable Configuration Bit To Timer0 (Figure 6-4) 0 1 MUX PSA WDT Time-out Note 1: TABLE 8-4: Address N/A T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
PIC10F220/222 8.8 FIGURE 8-9: Reset on Brown-out A Brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a Brown-out. BROWN-OUT PROTECTION CIRCUIT 3 VDD MCP809 VSS To reset PIC10F220/222 devices when a Brown-out occurs, external Brown-out protection circuits may be built, as shown in Figure 8-7 and Figure 8-8.
PIC10F220/222 8.9.2 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. 2. 3. An external Reset input on GP3/MCLR/VPP pin, when configured as MCLR. A Watchdog Timer Time-out Reset (if WDT was enabled). A change on input pin GP0, GP1 or GP3 when wake-up on change is enabled. These events cause a device Reset. The TO, PD GPWUF bits can be used to determine the cause of a device Reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up).
PIC10F220/222 NOTES: DS41270E-page 42 © 2007 Microchip Technology Inc.
PIC10F220/222 9.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories. • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction.
PIC10F220/222 TABLE 9-2: INSTRUCTION SET SUMMARY Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF BCF BSF BTFSC BTFSS ANDLW CALL CLRWDT GOTO IORLW MOVLW OPTION RETLW SLEEP TRIS XORLW Note 1: 2: 3: 4: 12-Bit Opcode Description Cycles MSb LSb Status Notes Affected f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d 0001 11df ffff C,DC,Z Add W and f 1 1,2,4 0001 01df ffff AND W with f 1 Z 2,4 0000 011f ffff C
PIC10F220/222 9.1 Instruction Description ADDWF Add W and f BCF Bit Clear f Syntax: [ label ] ADDWF Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 0≤b≤7 Operation: (W) + (f) → (destination) Operation: 0 → (f) Status Affected: C, DC, Z Status Affected: None Description: Description: Bit ‘b’ in register ‘f’ is cleared.
PIC10F220/222 BTFSS Bit Test f, Skip if Set CLRW Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRW 0 ≤ f ≤ 31 0≤b<7 Operands: None Operation: 00h → (W); 1→Z Operands: Clear W Operation: skip if (f) = 1 Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped.
PIC10F220/222 DECF Decrement f INCF Syntax: [ label ] DECF f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) – 1 → (dest) Operation: (f) + 1 → (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: The contents of register ‘f’ are incremented.
PIC10F220/222 IORWF Inclusive OR W with f MOVWF Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 Operation: (W).OR. (f) → (dest) (W) → (f) Operation: Status Affected: None Status Affected: Z Description: Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Move data from the W register to register ‘f’.
PIC10F220/222 RETLW Return with Literal in W SLEEP Enter SLEEP Mode Syntax: [ label ] Syntax: [label] Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W); TOS → PC Operation: 00h → WDT; 0 → WDT prescaler; 1 → TO; 0 → PD RETLW k SLEEP Status Affected: None Description: The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
PIC10F220/222 TRIS Load TRIS Register Syntax: [ label ] TRIS f Operands: f=6 Operation: (W) → TRIS register f Status Affected: None Description: TRIS register ‘f’ (f = 6 or 7) is loaded with the contents of the W register XORLW Exclusive OR literal with W Syntax: [label] Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC10F220/222 10.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature ...............................................................................................................................-65°C to +150°C Voltage on VDD with respect to VSS ...................................................................................
PIC10F220/222 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 10-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 8 10 20 25 Frequency (MHz) DS41270E-page 52 © 2007 Microchip Technology Inc.
PIC10F220/222 10.1 DC Characteristics: PIC10F220/222 (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40×C ≤ TA ≤ +85°C (industrial) DC CHARACTERISTICS Param No. Sym Characteristic Min Typ(1) Max Units Conditions D001 VDD Supply Voltage 2.0 5.5 V See Figure 10-1 D002 VDR RAM Data Retention Voltage(2) 1.
PIC10F220/222 10.2 DC Characteristics: PIC10F220/222 (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40×C £ TA £ +125×C (extended) DC CHARACTERISTICS Param No. Sym Characteristic Min Typ(1) Max Units Conditions D001 VDD Supply Voltage 2.0 5.5 V See Figure 10-1 D002 VDR RAM Data Retention Voltage(2) 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure Power-on Reset V IDD D022 * Note 1: 2: 3: 4: — — — — — 175 0.
PIC10F220/222 10.3 DC Characteristics: PIC10F220/222 (Industrial, Extended) DC CHARACTERISTICS Param No. Sym VIL Characteristic Standard Operating Conditions (unless otherwise specified) Operating temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Operating voltage VDD range as described in DC specification Min Typ† Max Units Conditions Input Low Voltage I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer MCLR, T0CKI D032 VIH Vss — 0.
PIC10F220/222 TABLE 10-1: VDD (Volts) GP0/GP1 2.0 5.5 GP3 2.0 5.5 DS41270E-page 56 PULL-UP RESISTOR RANGES Temperature (°C) Min Typ Max Units -40 25 85 125 -40 25 85 125 73K 73K 82K 86K 15K 15K 19K 23K 105K 113K 123K 132k 21K 22K 26k 29K 186K 187K 190K 190K 33K 34K 35K 35K Ω Ω Ω Ω Ω Ω Ω Ω -40 25 85 125 -40 25 85 125 63K 77K 82K 86K 16K 16K 24K 26K 81K 93K 96k 100K 20k 21K 25k 27K 96K 116K 116K 119K 22K 23K 28K 29K Ω Ω Ω Ω Ω Ω Ω Ω © 2007 Microchip Technology Inc.
PIC10F220/222 10.4 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC10F220/222 FIGURE 10-3: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING VDD MCLR 30 Internal POR 32 32 32 DRT Timeout(2) Internal Reset Watchdog Timer Reset 31 34 34 I/O pin(1) Note 1: 2: I/O pins must be taken out of High-impedance mode by enabling the output drivers in software. Runs on POR Reset only.
PIC10F220/222 FIGURE 10-4: TIMER0 CLOCK TIMINGS T0CKI 40 41 42 TABLE 10-4: TIMER0 CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) AC CHARACTERISTICS Param Sym No. Characteristic 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width 42 Tt0P T0CKI Period * Note 1: No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5 TCY + 20* 10* 0.
PIC10F220/222 TABLE 10-5: A/D CONVERTER CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym No. Characteristic Min Typ† Max Units 8 bits bit Conditions A01 NR Resolution — — A03 EIL Integral Error — — ±1.5 LSb A04 EDL Differential Error — — -1 < EDL ≤ + 1.5 LSb A05 EFS Full-scale Range 2.0* — 5.5* V A06 EOFF Offset Error — — ±1.5 LSb A07 EGN Gain Error — — ±1.
PIC10F220/222 11.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC10F220/222 FIGURE 11-2: IDD vs. VDD OVER FOSC (8 MHZ) Typical (Sleep Mode all Peripherals Disabled) 1,800 1,600 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) Maximum 1,400 8 MHz IDD (μA) 1,200 1,000 Typical 800 8 MHz 600 400 200 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 11-3: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 1.10 Typical: Statistical Mean @25°C 1.00 0.
PIC10F220/222 FIGURE 11-4: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 16.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 14.0 Max. 125°C IPD (μA) 12.0 10.0 8.0 6.0 4.0 Max. 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) TYPICAL WDT IPD vs. VDD FIGURE 11-5: 9 8 Typical: Statistical Mean @25°C 7 IPD (μA) 6 5 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC10F220/222 FIGURE 11-6: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 20.0 IPD (μA) Max. 125°C 15.0 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 11-7: WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER) 50 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) Max. 125°C 45 40 Max. 85°C 35 Time (ms) 30 Typical. 25°C 25 20 Min. -40°C 15 10 5 0 2.0 2.5 3.0 3.
PIC10F220/222 FIGURE 11-8: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 0.7 Max. 125°C 0.6 VOL (V) 0.5 Max. 85°C 0.4 Typical 25°C 0.3 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 11-9: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.
PIC10F220/222 FIGURE 11-10: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.0 1.5 1.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 11-11: (VDD = 5.0V) VOH vs. IOH OVER TEMPERATURE ( , ) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.
PIC10F220/222 FIGURE 11-12: TTL INPUT THRESHOLD VIN vs. VDD (TTL Input, -40×C TO 125×C) 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) Max. -40°C VIN (V) 1.3 Typ. 25°C 1.1 Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 11-13: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) VIH Min.
PIC10F220/222 NOTES: DS41270E-page 68 © 2007 Microchip Technology Inc.
PIC10F220/222 12.
PIC10F220/222 12.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC10F220/222 12.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC10F220/222 12.11 PICSTART Plus Development Programmer 12.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC10F220/222 13.0 PACKAGING INFORMATION 13.1 Package Marking Information 6-Lead SOT-23* XXNN 8-Lead PDIP XXXXXXXX XXXXXNNN YYWW 8-Lead DFN* XXX YWW NN Legend: XX...
PIC10F220/222 TABLE 13-1: 8-LEAD 2x3 DFN (MC) TOP MARKING Part Number Marking TABLE 13-2: 6-LEAD SOT-23 (OT) PACKAGE TOP MARKING Part Number Marking PIC10F220-I/MC BJ0 PIC10F220-I/OT 20NN PIC10F220-E/MC BK0 PIC10F220-E/OT A0NN PIC10F222-I/MC BL0 PIC10F222-I/OT 22NN PIC10F222-E/MC BM0 PIC10F222-E/OT Note: DS41270E-page 74 A2NN NN represents traceability code. the alphanumeric © 2007 Microchip Technology Inc.
PIC10F220/222 6-Lead Plastic Small Outline Transistor (OT) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging b 4 N E E1 PIN 1 ID BY LASER MARK 1 2 3 e e1 D A A2 c φ L A1 L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 6 Pitch e 0.95 BSC Outside Lead Pitch e1 1.90 BSC Overall Height A 0.90 – Molded Package Thickness A2 0.89 – 1.45 1.30 Standoff A1 0.
PIC10F220/222 8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 8 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .
PIC10F220/222 8-Lead Plastic Dual Flat, No Lead Package (MC) – 2x3x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e b N N L K E2 E EXPOSED PAD NOTE 1 2 1 2 NOTE 1 1 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.
PIC10F220/222 APPENDIX A: REVISION HISTORY Revision A Original release of document. Revision B (03/2006) Table 3-1, GP1; Section 4.7, Program Counter; Table 52; Figure 8-5; Section 9.1, ANDWF, SLEEP, SUBWF, SWAPF, XORLW. Revision C (08/2006) Added 8-Lead DFN pinout diagram, updated Table 1-1 with DFN package, updated Table 10-3 in Section 10.0, added 8-Lead DFN package marking information to section 13.0, updated the Product Identification System section to include DFN package identification.
PIC10F220/222 INDEX A M A/D Specifications.............................................................. 60 ADC Internal Sampling Switch (RSS) IMPEDANCE ................ 32 Source Impedance...................................................... 32 ALU ....................................................................................... 9 Assembler MPASM Assembler..................................................... 62 B Block Diagram On-Chip Reset Circuit ................................................
PIC10F220/222 W Wake-up from Sleep ........................................................... 41 Watchdog Timer (WDT) ................................................ 33, 38 Period.......................................................................... 38 Programming Considerations ..................................... 38 WWW Address.................................................................... 75 WWW, On-Line Support........................................................ 3 Z Zero bit ...........
PIC10F220/222 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC10F220/222 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC10F220/222 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: PIC10F220 PIC10F222 PIC10F220T (Tape & Reel) PIC10F222T (Tape & Reel) Temperature Range: I E = -40°C to +85°C = -40°C to +125°C Package: P OT MC = = = Pattern: Special Requirements c) PIC10F220-I/P = Industrial temp.
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