Datasheet

© 2007 Microchip Technology Inc. DS41239D-page 47
PIC10F200/202/204/206
FIGURE 9-6: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
N/A OPTION
GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, – = unimplemented, read as ‘0’, u = unchanged.
(Figure 6-5)
Postscaler
WDT Time-out
Watchdog
Time
From Timer0 Clock Source
WDT Enable
Configuration
Bit
PSA
Postscaler
8-to-1 MUX
PS<2:0>
(Figure 6-4)
To Timer0
0
1
M
U
X
1
0
PSA
MUX