PIC10F200/202/204/206 Data Sheet 6-Pin, 8-bit Flash Microcontrollers © 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC10F200/202/204/206 6-Pin, 8-Bit Flash Microcontrollers Devices Included In This Data Sheet: • PIC10F200 • PIC10F204 • PIC10F202 • PIC10F206 Low-Power Features/CMOS Technology: • Operating Current: - < 175 μA @ 2V, 4 MHz, typical • Standby Current: - 100 nA @ 2V, typical • Low-power, high-speed Flash technology: - 100,000 Flash endurance - > 40 year retention • Fully static design • Wide operating voltage range: 2.0V to 5.
PIC10F200/202/204/206 1 VSS 2 GP1/ICSPCLK 3 GP0/ICSPDAT/CIN+ 1 VSS 2 GP1/ICSPCLK/CIN- 3 PIC10F200/202 GP0/ICSPDAT 6 GP3/MCLR/VPP 5 VDD 4 GP2/T0CKI/FOSC4 PIC10F204/206 SOT-23 Pin Diagrams 6 GP3/MCLR/VPP 5 VDD GP2/T0CKI/COUT/FOSC4 4 1 VDD 2 GP2/T0CKI/FOSC4 3 GP1/ICSPCLK 4 N/C 1 VDD 2 GP2/T0CKI/COUT/FOSC4 3 GP1/ICSPCLK/CIN- 4 PIC10F204/206 N/C PIC10F200/202 8-Pin PDIP Pin Diagrams 8 GP3/MCLR/VPP 7 VSS 6 N/C 5 GP0/ICSPDAT 8 GP3/MCLR/VPP 7 VSS 6 N/C 5 GP
PIC10F200/202/204/206 Table of Contents 1.0 General Description...................................................................................................................................................................... 5 2.0 PIC10F200/202/204/206 Device Varieties .................................................................................................................................. 7 3.0 Architectural Overview .............................................................................
PIC10F200/202/204/206 NOTES: DS41239D-page 4 © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 1.0 GENERAL DESCRIPTION 1.1 Applications The PIC10F200/202/204/206 devices fit in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The Flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient.
PIC10F200/202/204/206 NOTES: DS41239D-page 6 © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 2.0 PIC10F200/202/204/206 DEVICE VARIETIES A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC10F200/202/204/206 Product Identification System at the back of this data sheet to specify the correct part number. 2.1 Quick Turn Programming (QTP) Devices 2.
PIC10F200/202/204/206 NOTES: DS41239D-page 8 © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC10F200/202/204/206 devices can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC10F200/202/204/206 devices use a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus.
PIC10F200/202/204/206 FIGURE 3-1: PIC10F200/202 BLOCK DIAGRAM 9-10 512 x12 or 256 x12 24 or 16 bytes File Registers Stack 1 Stack 2 12 RAM Addr GPIO GP0/ICSPDAT GP1/ICSPCLK GP2/T0CKI/FOSC4 GP3/MCLR/VPP RAM Program Memory Program Bus 8 Data Bus Program Counter Flash 9 Addr MUX Instruction Reg Direct Addr 5 5-7 Indirect Addr FSR Reg STATUS Reg 8 3 Device Reset Timer Instruction Decode & Control Timing Generation Power-on Reset Watchdog Timer Internal RC Clock MUX ALU 8 W Reg Timer0 M
PIC10F200/202/204/206 FIGURE 3-2: PIC10F204/206 BLOCK DIAGRAM 9-10 512 x12 or 256 x12 GPIO GP0/ICSPDAT/CIN+ GP1/ICSPCLK/CINGP2/T0CKI/COUT/FOSC4 GP3/MCLR/VPP RAM Program Memory Program Bus 8 Data Bus Program Counter Flash 24 or 16 bytes Stack 1 Stack 2 File Registers 12 RAM Addr 9 Addr MUX Instruction Reg Direct Addr 5 5-7 Indirect Addr FSR Reg STATUS Reg 8 3 Device Reset Timer Instruction Decode & Control Timing Generation Power-on Reset Watchdog Timer Internal RC Clock MUX ALU 8 W
PIC10F200/202/204/206 TABLE 3-2: PIC10F200/202/204/206 PINOUT DESCRIPTION Name GP0/ICSPDAT/CIN+ GP1/ICSPCLK/CIN- GP2/T0CKI/COUT/ FOSC4 GP3/MCLR/VPP Function Input Type Output Type GP0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin. — Description CIN+ AN GP1 TTL CMOS Bidirectional I/O pin.
PIC10F200/202/204/206 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g.
PIC10F200/202/204/206 NOTES: DS41239D-page 14 © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 4.0 MEMORY ORGANIZATION The PIC10F200/202/204/206 memories are organized into program memory and data memory. Data memory banks are accessed using the File Select Register (FSR). 4.1 FIGURE 4-1: PC<7:0> 9 CALL, RETLW Stack Level 1 Stack Level 2 Program Memory Organization for the PIC10F200/204 The PIC10F200/204 devices have a 9-bit Program Counter (PC) capable of addressing a 512 x 12 program memory space.
PIC10F200/202/204/206 4.2 Program Memory Organization for the PIC10F202/206 The PIC10F202/206 devices have a 10-bit Program Counter (PC) capable of addressing a 1024 x 12 program memory space. Only the first 512 x 12 (0000h-01FFh) for the PIC10F202/206 are physically implemented (see Figure 4-2). Accessing a location above these boundaries will cause a wraparound within the first 512 x 12 space (PIC10F202/206). The effective Reset vector is at 0000h (see Figure 4-2).
PIC10F200/202/204/206 FIGURE 4-3: PIC10F200/204 REGISTER FILE MAP FIGURE 4-4: PIC10F202/206 REGISTER FILE MAP File Address File Address 00h INDF(1) TMR0 01h TMR0 02h PCL 02h PCL 03h STATUS 03h STATUS 04h FSR 04h FSR 05h OSCCAL 05h OSCCAL 06h GPIO 06h GPIO 07h CMCON0(2) 07h CMCON0(2) 00h 01h INDF (1) 08h 08h Unimplemented(3) General Purpose Registers 0Fh 10h General Purpose Registers 1Fh 1Fh Note 1: Not a physical register. See Section 4.
PIC10F200/202/204/206 4.3.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.
PIC10F200/202/204/206 4.4 STATUS Register This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC10F200/202/204/206 4.5 OPTION Register The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION<7:0> bits. REGISTER 4-2: Note: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin (i.e.
PIC10F200/202/204/206 4.6 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal precision 4 MHz oscillator. It contains seven bits for calibration. Note: Erasing the device will also erase the preprogrammed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. After you move in the calibration constant, do not change the value. See Section 9.2.
PIC10F200/202/204/206 4.7 Program Counter 4.7.1 As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The Program Counter Low (PCL) is mapped to PC<7:0>.
PIC10F200/202/204/206 4.9 Indirect Data Addressing: INDF and FSR Registers EXAMPLE 4-1: The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. 4.
PIC10F200/202/204/206 NOTES: DS41239D-page 24 © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 5.0 I/O PORT 5.3 As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g., MOVF GPIO, W) always read the I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance) since the I/O control registers are all set. 5.1 GPIO GPIO is an 8-bit I/O register. Only the low-order 4 bits are used (GP<3:0>).
PIC10F200/202/204/206 TABLE 5-2: Address N/A SUMMARY OF PORT REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 TRISGPIO — — — — Bit 3 Bit 2 Bit 1 Bit 0 I/O Control Register Value on Power-On Reset Value on All Other Resets ---- 1111 ---- 1111 N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 03h STATUS GPWUF CWUF — TO PD Z DC C 00-1 1xxx qq-q quuu(1), (2) 06h GPIO — — — — GP3 GP2 GP1 GP0 ---- xxxx ---- uuuu Legend: Note 1: 2: 5.4 5.4.
PIC10F200/202/204/206 FIGURE 5-2: SUCCESSIVE I/O OPERATION (PIC10F200/202/204/206) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Instruction Fetched PC MOVWF GPIO PC + 1 MOVF GPIO, W Q1 Q2 Q3 Q4 PC + 2 PC + 3 This example shows a write to GPIO followed by a read from GPIO. NOP NOP Data setup time = (0.25 TCY – TPD) where: TCY = instruction cycle GP<2:0> TPD = propagation delay Port pin written here Instruction Executed MOVWF GPIO (Write to GPIO) © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 NOTES: DS41239D-page 28 © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 6.0 TIMER0 MODULE AND TMR0 REGISTER (PIC10F200/202) Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1 “Using Timer0 with an External Clock (PIC10F200/202)”.
PIC10F200/202/204/206 FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC (Program Counter) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Instruction Fetch MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W PC – 1 T0 Timer0 PC PC + 3 PC + 4 PC + 5 NT0 Write TMR0 executed TABLE 6-1: 01h PC + 2 T0 + 1 Instruction Executed Address PC + 1 Read TMR0 reads NT0 PC + 6 NT0 + 1 Read TMR0 reads NT0 Read TMR0 Read TMR
PIC10F200/202/204/206 6.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-4 shows the delay from the external clock edge to the timer incrementing.
PIC10F200/202/204/206 EXAMPLE 6-2: To change the prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler.
PIC10F200/202/204/206 7.0 TIMER0 MODULE AND TMR0 REGISTER (PIC10F204/206) The second Counter mode uses the output of the comparator to increment Timer0. It can be entered in two different ways. The first way is selected by setting the T0CS bit (OPTION<5>) and clearing the CMPT0CS bit (CMCON<4>); (COUTEN [CMCON<6>]) does not affect this mode of operation. This enables an internal connection between the comparator and the Timer0.
PIC10F200/202/204/206 FIGURE 7-2: PC (Program Counter) TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC – 1 Instruction Fetch PC PC + 1 MOVWF TMR0 T0 Timer0 T0 + 1 PC + 3 T0 + 2 Instruction Executed Write TMR0 executed FIGURE 7-3: PC + 2 PC + 4 PC+5 PC + 6 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W NT0 + 1 NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 NT0 + 2 Read TMR0 Read TMR
PIC10F200/202/204/206 7.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-4 shows the delay from the external clock edge to the timer incrementing.
PIC10F200/202/204/206 EXAMPLE 7-2: CHANGING PRESCALER (WDT→TIMER0) CLRWDT MOVLW ‘xxxx0xxx’ ;Clear WDT and ;prescaler ;Select TMR0, new ;prescale value and ;clock source OPTION FIGURE 7-5: GP2/T0CKI Pin BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER (2) TCY (= FOSC/4) Data Bus 8 0 1 Comparator Output 1 M U X 1 M U X 0 0 T0SE(1) T0CS(1) Sync 2 Cycles TMR0 Reg PSA(1) CMPT0CS(3) 0 Watchdog Timer M U X 1 8-bit Prescaler 8 8-to-1 MUX PS<2:0>(1) PSA(1) WDT Enable bit 1 0 MUX PSA(1) WDT Ti
PIC10F200/202/204/206 8.0 COMPARATOR MODULE The comparator module contains one Analog comparator. The inputs to the comparator are multiplexed with GP0 and GP1 pins. The output of the comparator can be placed on GP2. The CMCON0 register, shown in Register 8-1, controls the comparator operation. A block diagram of the comparator is shown in Figure 8-1.
PIC10F200/202/204/206 8.1 Comparator Configuration The on-board comparator inputs, (GP0/CIN+, GP1/ CIN-), as well as the comparator output (GP2/COUT), are steerable. The CMCON0, OPTION and TRIS registers are used to steer these pins (see Figure 8-1). If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Table 12-1. FIGURE 8-1: Note: The comparator can have an inverted output (see Figure 8-1).
PIC10F200/202/204/206 8.2 Comparator Operation 8.5 A single comparator is shown in Figure 8-2 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
PIC10F200/202/204/206 FIGURE 8-3: ANALOG INPUT MODE VDD VT = 0.6V RS < 10 kΩ RIC AIN CPIN 5 pF VA ILEAKAGE ±500 nA VT = 0.
PIC10F200/202/204/206 9.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits that deal with the needs of realtime applications. The PIC10F200/202/204/206 microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide powersaving operating modes and offer code protection.
PIC10F200/202/204/206 9.2 Oscillator Configurations 9.2.1 9.3 OSCILLATOR TYPES The PIC10F200/202/204/206 devices are offered with Internal Oscillator mode only. • INTOSC: Internal 4 MHz Oscillator 9.2.2 INTERNAL 4 MHz OSCILLATOR The internal oscillator provides a 4 MHz (nominal) system clock (see Section 12.0 “Electrical Characteristics” for information on variation over voltage and temperature).
PIC10F200/202/204/206 TABLE 9-2: RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr: 03h PCL Addr: 02h Power-on Reset 00-1 1xxx 1111 1111 MCLR Reset during normal operation 000u uuuu 1111 1111 MCLR Reset during Sleep 0001 0uuu 1111 1111 WDT Reset during Sleep 0000 0uuu 1111 1111 WDT Reset normal operation 0000 uuuu 1111 1111 Wake-up from Sleep on pin change 1001 0uuu 1111 1111 Wake-up from Sleep on comparator change 0101 0uuu 1111 1111 Legend: u = unchanged, x = unknown, – = unimpleme
PIC10F200/202/204/206 FIGURE 9-2: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) GP3/MCLR/VPP MCLR Reset MCLRE WDT Reset WDT Time-out S Q R Q Start-up Timer CHIP Reset (10 μs or 18 ms) Pin Change Sleep Wake-up on pin change Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) FIGURE 9-3: VDD MCLR Internal POR TDRT DRT Time-out Internal Reset FIGURE 9-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR Internal PO
PIC10F200/202/204/206 FIGURE 9-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min. © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 9.5 Device Reset Timer (DRT) On the PIC10F200/202/204/206 devices, the DRT runs any time the device is powered up. The DRT operates on an internal oscillator. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the oscillator to stabilize. The on-chip DRT keeps the devices in a Reset condition for approximately 18 ms after MCLR has reached a logic high (VIH MCLR) level.
PIC10F200/202/204/206 FIGURE 9-6: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure 6-5) 0 Watchdog Time 1 M U X Postscaler 8-to-1 MUX PS<2:0> PSA WDT Enable Configuration Bit To Timer0 (Figure 6-4) 0 1 MUX PSA WDT Time-out TABLE 9-4: Address N/A SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Name OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 Value on Power-On Reset Value on All Other Resets 1111 1111 1111 11
PIC10F200/202/204/206 9.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF, CWUF) The TO, PD, GPWUF and CWUF bits in the STATUS register can be tested to determine if a Reset condition has been caused by a power-up condition, a MCLR, Watchdog Timer (WDT) Reset, wake-up on comparator change or wake-up on pin change.
PIC10F200/202/204/206 FIGURE 9-9: BROWN-OUT PROTECTION CIRCUIT 3 VDD MCP809 VSS Bypass Capacitor 2. MCLR 3. PIC10F20X 4. Note: 9.9 This brown-out protection circuit employs Microchip Technology’s MCP809 microcontroller supervisor. There are 7 different trip point selections to accommodate 5V to 3V systems. Power-Down Mode (Sleep) A device may be powered down (Sleep) and later powered up (wake-up from Sleep). 9.9.1 SLEEP An external Reset input on GP3/MCLR/VPP pin, when configured as MCLR.
PIC10F200/202/204/206 9.10 Program Verification/Code Protection FIGURE 9-10: If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. The first 64 locations and the last location (Reset vector) can be read, regardless of the code protection bit setting. 9.11 ID Locations Four memory locations are designated as ID locations where the user can store checksum or other code identification numbers.
PIC10F200/202/204/206 10.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories. • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 12-bit word divided into an opcode, which specifies the instruction type and one or more operands which further specify the operation of the instruction.
PIC10F200/202/204/206 TABLE 10-2: Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF INSTRUCTION SET SUMMARY Description Cycles 12-Bit Opcode MSb LSb Status Notes Affected f, d f, d f — f, d f, d f, d f, d f, d f, d f, d f — f, d f, d f, d f, d f, d 0001 11df ffff C, DC, Z 1, 2, 4 Add W and f 1 0001 01df ffff AND W with f 1 Z 2, 4 0000 011f ffff Clear f 1 Z 4 0000 0100 0000 Clear W 1 Z 0010 01df ffff Complement f 1 Z 0000 11df ffff Dec
PIC10F200/202/204/206 ADDWF Add W and f BCF Bit Clear f Syntax: [ label ] ADDWF Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 0≤b≤7 Operation: (W) + (f) → (dest) Operation: 0 → (f) Status Affected: C, DC, Z Status Affected: None Description: Description: Bit ‘b’ in register ‘f’ is cleared. BSF Bit Set f ANDLW Syntax: f,d Add the contents of the W register and register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
PIC10F200/202/204/206 BTFSS Bit Test f, Skip if Set CLRW Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRW 0 ≤ f ≤ 31 0≤b<7 Operands: None Operation: 00h → (W); 1→Z Operands: Clear W Operation: skip if (f) = 1 Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped.
PIC10F200/202/204/206 DECF Decrement f INCF Syntax: [ label ] DECF f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) – 1 → (dest) Operation: (f) + 1 → (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: The contents of register ‘f’ are incremented.
PIC10F200/202/204/206 IORWF Inclusive OR W with f MOVWF Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 (W).OR. (f) → (dest) Operation: (W) → (f) Operation: Status Affected: None Status Affected: Z Description: Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Move data from the W register to register ‘f’.
PIC10F200/202/204/206 RETLW Return with literal in W SLEEP Enter SLEEP Mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W); TOS → PC Operation: Status Affected: None Description: The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
PIC10F200/202/204/206 TRIS Load TRIS Register XORWF Syntax: [ label ] TRIS Syntax: [ label ] XORWF Operands: f=6 Operands: Operation: (W) → TRIS register f 0 ≤ f ≤ 31 d ∈ [0,1] f Exclusive OR W with f f,d Status Affected: None Operation: (W) .XOR. (f) → (dest) Description: TRIS register ‘f’ (f = 6 or 7) is loaded with the contents of the W register Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’.
PIC10F200/202/204/206 11.
PIC10F200/202/204/206 11.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC10F200/202/204/206 11.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC10F200/202/204/206 11.11 PICSTART Plus Development Programmer 11.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC10F200/202/204/206 12.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.......................................................................................................... -40°C to +125°C Storage temperature ............................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ...............................................................................
PIC10F200/202/204/206 PIC10F200/202/204/206 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 12-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) DS41239D-page 64 © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 12.1 DC Characteristics: PIC10F200/202/204/206 (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40×C ≤ TA ≤ +85°C (industrial) DC CHARACTERISTICS Param No. Sym Characteristic Min Typ(1) Max Units Conditions D001 VDD Supply Voltage 2.0 5.5 V See Figure 12-1 D002 VDR RAM Data Retention Voltage(2) 1.
PIC10F200/202/204/206 12.2 DC Characteristics: PIC10F200/202/204/206 (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40×C £ TA £ +125×C (extended) DC CHARACTERISTICS Param No. Sym Characteristic Min Typ(1) Max Units Conditions D001 VDD Supply Voltage 2.0 5.5 V See Figure 12-1 D002 VDR RAM Data Retention Voltage(2) 1.
PIC10F200/202/204/206 12.3 DC Characteristics: PIC10F200/202/204/206 (Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Operating voltage VDD range as described in DC specification DC CHARACTERISTICS Param No.
PIC10F200/202/204/206 TABLE 12-1: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristics Min Typ† Max Units D300 VOS Input Offset Voltage — ± 5.0 ± 10 mV D301 VCM Input Common Mode Voltage 0 — VDD–1.
PIC10F200/202/204/206 12.4 Timing Parameter Symbology and Load Conditions – PIC10F200/202/204/206 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC10F200/202/204/206 TABLE 12-3: CALIBRATED INTERNAL RC FREQUENCIES – PIC10F200/202/204/206 AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 12.1 “DC Characteristics”. Param No. Freq Min Tolerance F10 Sym FOSC Characteristic Internal Calibrated INTOSC Frequency(1,2) Typ† Max Units Conditions ± 1% 3.96 4.00 4.04 MHz VDD=3.
PIC10F200/202/204/206 TABLE 12-4: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC10F200/202/204/206 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section 12.1 “DC Characteristics” AC CHARACTERISTICS Param No. Sym Characteristic Min Typ(1) Max Units Conditions 30 TMCL MCLR Pulse Width (low) 2* 5* — — — — μs μs VDD = 5V, -40°C to +85°C VDD = 5.
PIC10F200/202/204/206 NOTES: DS41239D-page 72 © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC10F200/202/204/206 FIGURE 13-2: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 0.40 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 0.35 IPD (μA) 0.30 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-3: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 16.
PIC10F200/202/204/206 FIGURE 13-4: 80 COMPARATOR IPD vs. VDD (COMPARATOR ENABLED) Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) Maximum IPD (μA) 60 Typical 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 4.0 4.5 5.0 5.5 VDD (V) TYPICAL WDT IPD vs. VDD FIGURE 13-5: 9 8 7 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) IPD (μA) 6 5 4 3 2 1 0 2.0 2.5 3.0 3.5 VDD (V) © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 FIGURE 13-6: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 20.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) IPD (μA) Max. 125°C 15.0 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-7: WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER) 50 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) Max. 125°C 45 40 Max. 85°C 35 Time (ms) 30 Typical.
PIC10F200/202/204/206 FIGURE 13-8: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 0.7 Max. 125°C 0.6 VOL (V) 0.5 Max. 85°C 0.4 Typical 25°C 0.3 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 13-9: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.
PIC10F200/202/204/206 FIGURE 13-10: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.0 1.5 1.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 13-11: (VDD = 5.0V) VOH vs. IOH OVER TEMPERATURE ( , ) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.
PIC10F200/202/204/206 FIGURE 13-12: TTL INPUT THRESHOLD VIN vs. VDD (TTL Input, -40×C TO 125×C) 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) Max. -40°C VIN (V) 1.3 Typ. 25°C 1.1 Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-13: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C 3.
PIC10F200/202/204/206 FIGURE 13-14: INTOSC (INTERNAL OSCILLATOR) POWERUP TIMES vs. VDD Maximum (Sleep Mode all Peripherals Disabled) 45 Powerup Time (ms) 40 35 Max. 125°C 30 25 Max. 85°C 20 Typical 25°C 15 Max. -40°C 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41239D-page 80 © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 14.0 PACKAGING INFORMATION 14.1 Package Marking Information 6-Lead SOT-23A* XXNN 8-Lead PDIP XXXXXXXX XXXXXNNN YYWW 8-Lead 2x3 DFN* XXX YWW NN 02JR Example PIC10F202 I/P e3 07Q 0520 Example BE0 610 17 Legend: XX...
PIC10F200/202/204/206 TABLE 14-1: 8-LEAD 2x3 DFN (MC) TOP MARKING Part Number PIC10F200-I/MC Marking TABLE 14-2: 6-LEAD SOT-23 (OT) PACKAGE TOP MARKING Part Number Marking BA0 PIC10F200-I/OT 00NN PIC10F200-E/MC BB0 PIC10F200-E/OT 00NN PIC10F202-I/MC BC0 PIC10F202-I/OT 02NN PIC10F202-E/MC BD0 PIC10F202-E/OT 02NN PIC10F204-I/MC BE0 PIC10F204-I/OT 04NN PIC10F204-E/MC BF0 PIC10F204-E/OT 04NN PIC10F206-I/MC BG0 PIC10F206-I/OT 06NN PIC10F206-E/MC BH0 PIC10F206-E/OT Note: DS41
PIC10F200/202/204/206 6-Lead Plastic Small Outline Transistor (OT) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging b 4 N E E1 PIN 1 ID BY LASER MARK 1 2 3 e e1 D A A2 c φ L A1 L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 6 Pitch e 0.95 BSC Outside Lead Pitch e1 1.90 BSC Overall Height A 0.90 – Molded Package Thickness A2 0.89 – 1.45 1.
PIC10F200/202/204/206 8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 8 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .
PIC10F200/202/204/206 8-Lead Plastic Dual Flat, No Lead Package (MC) – 2x3x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e b N N L K E2 E EXPOSED PAD NOTE 1 2 1 2 NOTE 1 1 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.
PIC10F200/202/204/206 NOTES: DS41239D-page 86 © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 APPENDIX A: REVISION HISTORY Revision C (August 2006) Added 8-Pin DFN Pin Diagram; Revised Table 1-1; Reformated all Registers; Revised Section 4.8 and added note; Section 5.3 (changed Figure reference to Figure 5-1); Tables 6-1 and 7-1 (removed shading from TRISGPIO (I/O Control Register); Sections 8.1-8.4 (changed Table reference to Table 12-2); Section 14.1 Revised and replaced Package Marking Information and drawings, Added Tables 14-1 & 14-2, Added DFN Package drawing.
PIC10F200/202/204/206 NOTES: DS41239D-page 88 © 2007 Microchip Technology Inc.
PIC10F200/202/204/206 INDEX A Assembler MPASM Assembler..................................................... 60 B Block Diagram On-Chip Reset Circuit ................................................. 44 Timer0................................................................... 29, 33 TMR0/WDT Prescaler..................................... 32, 36, 38 Watchdog Timer.......................................................... 47 Brown-Out Protection Circuit ..............................................
PIC10F200/202/204/206 W Wake-up from Sleep ........................................................... 49 Watchdog Timer (WDT) ................................................ 41, 46 Period.......................................................................... 46 Programming Considerations ..................................... 46 WWW Address.................................................................... 91 WWW, On-Line Support........................................................ 3 Z Zero bit ...
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