Datasheet

2004 Microchip Technology Inc. Preliminary DS41239A-page 69
PIC10F200/202/204/206
TABLE 12-1: DC CHARACTERISTICS: PIC10F200/202/204/206 (Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating temperature -40°C T
A +85°C (industrial)
-40°C T
A +125°C (extended)
Operating voltage V
DD range as described in DC specification
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
V
IL Input Low Voltage
I/O ports:
D030 with TTL buffer Vss 0.8V V For all 4.5 V
DD 5.5V
D030A Vss 0.15 V
DD V Otherwise
D031 with Schmitt Trigger
buffer
Vss 0.15 V
DD V
D032 MCLR
, T0CKI Vss 0.15 VDD V
V
IH Input High Voltage
I/O ports:
D040 with TTL buffer 2.0 V
DD V4.5 VDD 5.5V
D040A 0.25 V
DD
+ 0.8 VDD
—VDD V Otherwise
D041 with Schmitt Trigger
buffer
0.85 V
DD —VDD V For entire VDD range
D042 MCLR
, T0CKI 0.85 VDD —VDD V
D070 I
PUR GPIO weak pull-up current
(3)
TBD 250 TBD µAVDD = 5V, VPIN = VSS
IIL Input Leakage Current
(1, 2)
D060 I/O ports ± 1 µA Vss VPIN VDD, Pin at high-impedance
D061 GP3/MCLR
(4)
——± 30µA Vss VPIN VDD
D061A GP3/MCLR
(5)
——± 5µA Vss VPIN VDD
Output Low Voltage
D080 I/O ports 0.6 V I
OL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D080A 0.6 V I
OL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
Output High Voltage
D090 I/O ports
(2)
VDD0.7 V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D090A V
DD – 0.7 V IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
Capacitive Loading Specs
on Output Pins
D101 All I/O pins 50* pF
Legend: TBD = To Be Determined.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
* These parameters are for design guidance only and are not tested.
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
2: Negative current is defined as coming out of the pin.
3: Does not include GP3. For GP3 see parameters D061 and D061A.
4: This specification applies to GP3/MCLR
configured as external MCLR and GP3/MCLR configured as input with internal
pull-up enabled.
5: This specification applies when GP3/MCLR
is configured as an input with pull-up disabled. The leakage current of the
MCLR
circuit is higher than the standard I/O logic.