Datasheet

 2004 Microchip Technology Inc. Preliminary DS41239A-page 37
PIC10F200/202/204/206
8.0 COMPARATOR MODULE
The Comparator module contains one analog
comparator. The inputs to the comparator are
multiplexed with GP0 and GP1 pins. The output of the
comparator can be placed on GP2.
The CMCON0 register, shown in Register 8-1, controls
the comparator operation. A block diagram of the
comparator is shown in Figure 8-1.
REGISTER 8-1: CMCON0 REGISTER (ADDRESS: 07h)
R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
CMPOUT COUTEN
POL CMPT0CS CMPON CNREF CPREF CWU
bit 7 bit 0
bit 7 CMPOUT: Comparator Output bit
1 = VIN+ > VIN-
0 = V
IN+ < VIN-
bit 6 COUTEN: Comparator Output Enable bit
(1, 2)
1 = Output of comparator is NOT placed on the COUT pin
0 = Output of comparator is placed in the COUT pin
bit 5 POL: Comparator Output Polarity bit
(2)
1 = Output of comparator not inverted
0 = Output of comparator inverted
bit 4 CMPT0CS
: Comparator TMR0 Clock Source bit
(2)
1 = TMR0 clock source selected by T0CS control bit
0 = Comparator output used as TMR0 clock source
bit 3 CMPON: Comparator Enable bit
1 = Comparator is on
0 = Comparator is off
bit 2 CNREF: Comparator Negative Reference Select bit
(2)
1 = CIN- pin
(3)
0 = Internal voltage reference
bit 1 CPREF: Comparator Positive Reference Select bit
(2)
1 = CIN+ pin
(3)
0 = CIN- pin
(3)
bit 0 CWU: Comparator Wake-up on Change Enable bit
(2)
1 = Wake-up on comparator change is disabled
0 = Wake-up on comparator change is enabled.
Note 1: Overrides T0CS bit for TRIS control of GP2.
2: When the comparator is turned on, these control bits assert themselves. When the
comparator is off, these bits have no effect on the device operation and the other
control registers have precedence.
3: PIC10F204/206 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown