Datasheet

 2004-2013 Microchip Technology Inc. DS40001239E-page 45
PIC10F200/202/204/206
FIGURE 9-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
V1
Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1  V
DD min.