Datasheet
11Atmel LED Driver-MSL3162
PARAMETER SYMBOL CONDITIONS AND NOTES MIN TYP MAX UNIT
I²C SWITCHING CHARACTERISTICS
SCL clock frequency 1/t
SCL
Bus timeout disabled (Note 2) 0 1000 kHz
Bus timeout period t
TIMEOUT
OSCTRL = 0x04 (f
OSC
=20MHz); T
A
=25°C 27 30 33
ms
OSCTRL = 0x00 to 0x07; f
OSC
=16 to 23MHz 600000 / f
OSC
STOP to START condition bus
free time
t
BUF
0.5 µs
Repeated START condition hold
time
t
HD:STA
0.26 µs
Repeated START condition setup
time
t
SU:STA
0.26 µs
STOP condition setup time t
SU:STOP
0.26 µs
SDA data hold time t
HD:DAT
5 ns
SDA data valid acknowledge time t
VD:ACK
(Note 3) 0.05 0.55 µs
SDA data valid time t
VD:DAT
(Note 4) 0.05 0.55 µs
SDA data set-up time t
SU:DAT
100 ns
SCL clock low period t
LOW
0.5 µs
SCL clock high period t
HIGH
0.26 µs
SDA, SCL fall time t
F
(Note 5, Note 6) 120 ns
SDA, SCL rise time t
R
120 ns
SDA, SCL input suppression lter
period
t
SP
(Note 7, Note 10) 50 ns
Note 1. All parameters are tested at T
A
=25°C unless otherwise noted. Specifications at temperature are guaranteed by design
Note 2. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA
or SCL is held low for t
TIMEOUT
. Disable bus timeout feature for DC operation
Note 3. t
VD:ACK
= SCL low to SDA (out) low acknowledge time
Note 4. t
VD:DAT
= minimum SDA output data-valid time following SCL low transition
Note 5. A master device must internally provide an SDA hold time of at least 300ns to ensure an SCL low state
Note 6. The maximum SDA and SCL rise times are 300ns. The maximum SDA fall time is 250ns. This allows series protection resistors to be
connected between SDA and SCL inputs and the SDA/SCL bus lines without exceeding the maximum allowable rise time
Note 7. MSL3162 includes input filters on SDA, SCL, AD0, and AD1 inputs that suppress noise less than 50ns
Note 8. Subject to thermal dissipation characteristics of the device
Note 9. When mounted according to JEDEC, JEP149, and JESD51-12 for a two-layer PCB, θ
JA
= 18.6°C/W and θ
JC
= 1.4°C/W
Note 10. Guaranteed by design and characterization. Not production tested
PARAMETER CONDITIONS AND NOTES MIN TYP MAX UNIT
GSC frequency 0 5 MHz
High and low time PHI, GSC 40 ns
PWM frequency 20 50000 Hz
PWM duty cycle 0.5 100 %
PHI DLL lock cycles (Note 10) 4
PHI
cycles
Atmel LED Driver-MSL3162
16-string, RGB and White LED Drivers with Adaptive
Power Control and 1MHz I
2
C/SMBus Serial Interface