Datasheet

6
Atmel MSL3080 Datasheet
8 String 60mA LED Driver with Integrated Boost Controller
4.0 Electrical Characteristics
V
VIN
= 5V, V
EN
= 5V, Default Register Settings of Table 1, TA = -40°C to 85°C, unless otherwise noted. Typical values are at TA = +25°C
Parameter Conditions and Notes Min Typ Max Unit
DC Electrical Characteristics
VIN Operating Supply Voltage 4.5 5.5 V
VIN Operating Supply Current All STRn outputs 100% duty 18 mA
VIN Shutdown Supply Current EN = GND 1 µA
SDA, SCL, PWM, SYNC Input High Voltage 1.82 V
SDA, SCL, PWM, SYNC Input Low Voltage 0.72 V
Minimum PWM On-Time 400 ns
PWM, SYNC Input Frequency Range 20 200 50,000 Hz
SDA, FLTB Output Low Voltage Sinking 6mA 0.4 V
EN Threshold V
EN
rising 1.5 V
ILED Regulation Voltage Minimum R
ILED
= 60kΩ 1.25 V
STR0 to STR7 LED Regulation Current R
ILED
= 100kΩ, TA= 25°C V
STRn
= 1V 58.2 60.0 61.8 mA
STR0 to STR7 LED Current Load Regulation R
ILED
= 100kΩ V
STRn
= 1V to 5V 0.15 %/V
STR0 to STR7 LED Current Matching String to average of all strings -3 3 %
STR0 to STR7 Minimum Headroom V
STRn
= 60mA 0.5 V
STR0 to STR7 Short Circuit Fault Threshold R
SCTH
= 1.0kΩ 3.98 4.96 V
FB Feedback Output Current FBO DAC = 0xFF, V
FB
= 0 224 350 µA
FB Feedback Output Current Step Size 1.1 µA
FBI Input Disable Threshold 50 mV
Thermal shutdown temperature Temperature Rising, 10°C Hysteresis 135 °C
Boost Regulator Electrical Characteristics
Switching Frequency 569 665 762 kHz
Gate Voltage Rise/Fall Time C
GATE
= 1nF 50 ns
CS Current Limit Threshold Voltage 75 111 147 mV
Maximum Duty Cycle At factory set boost frequency 90.1 %
Minimum On Time
f
BOOST
= 350kHz to 1MHz (contact factory for boost frequencies different
from 625kHz)
241 300 ns
Boost Regulator Leading-Edge Blanking Period 130 ns
FB Regulation Voltage 2.4 2.5 2.6 V
I²C Switching Characteristics
SCL Clock Frequency 1/t
SCL
Bus timeout disabled (Note 1) 0 1000 kHz
Bus Timeout Period t
timeout
TA = 25°C (Note 7) 29 30 ms
STOP to START Condition Bus Free Time t
BUF
(Note 7) 0.5 µs
Repeated START condition Hold Time t
HD:STA
(Note 7) 0.26 µs
Repeated START condition Setup Time t
SU:STA
(Note 7) 0.26 µs
STOP Condition Setup Time t
SU:STOP
(Note 7) 0.26 µs
SDA Data Hold Time t
HD:DAT
(Note 7) 0 ns
SDA Data Valid Acknowledge Time t
VD:ACK
(Note 2) (Note 7) 0.05 0.55 µs
SDA Data Valid Time t
VD:DAT
(Note 3) (Note 7) 0.05 0.55 µs
SDA Data Set-Up Time t
SU:DAT
(Note 7) 100 ns
SCL Clock Low Period t
LOW
(Note 7) 0.5 µs
SCL Clock High Period t
HIGH
(Note 7) 0.26 µs
SDA, SCL Fall Time t
f
(Note 4) (Note 5) (Note 7) 120 ns
SDA, SCL Rise Time t
r
(Note 7) 120 ns
SDA, SCL Input Suppression Filter Period t
SP
(Note 6) (Note 7) 50 ns
Note 1. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low for timeout.
Note 2. tVD:ACK = SCL LOW to SDA (out) LOW acknowledge time.
Note 3. t
VD:DAT
= minimum SDA output data-valid time following SCL LOW transition.
Note 4. A master device must internally provide an SDA hold time of at least 300ns to ensure an SCL low state.
Note 5. The maximum SDA and SCL rise times is 300ns. The maximum SDA fall time is 250ns. This allows series protection resistors to be connected between SDA and SCL inputs and
the SDA/SCL bus lines without exceeding the maximum allowable rise time.
Note 6. MSL3080 include input lters on SDA and SCL that suppress input noise less than 50ns
Note 7. Parameter is guaranteed by design and not production tested.
Note 8. Per JEDEC specication JESD51-5 and JESD51-12.
Note 9. Tests performed at TA = 25°C, specications over temperature guaranteed by design.