Datasheet

17Atmel LED Drivers-MSL2160/MSL2161
PARAMETER SYMBOL CONDITIONS AND NOTES MIN TYP MAX UNIT
SCK Falling Edge to MISO Data Valid t
VALID
(Note 1) 20 ns
SCK High Time 20 ns
SCK Low Time 20 ns
MOSI, CSB, SCK Signal Rise Time t
R(SPI)
Receiving (Note 6) 5.0 ns
MOSI, CSB, SCK Signal Fall Time t
F(SPI)
Receiving (Note 6) 5.0 ns
MISO Signal Rise Time C
load
= 10pF (Note 6) 20 ns
MISO Signal Fall Time C
load
= 10pF (Note 6) 20 ns
PARAMETER SYMBOL CONDITIONS AND NOTES MIN TYP MAX UNIT
I²C TIMING CHARACTERISTICS, MSL2161
SCL Clock Frequency 1/t
SCL
I2CTOEN = 0 (Note 2) 0 1 MHz
Bus Timeout Period t
timeout
f
OSC
= 20MHz, T
A
= 25°C 29 30 31 ms
f
OSC
= 16MHz to 23MHz 600,000 / f
OSC
s
STOP to START Condition Bus Free Time t
BUF
0.5 µs
Repeated START condition Hold Time t
HD:STA
0.26 µs
Repeated START condition Setup Time t
SU:STA
0.26 µs
STOP Condition Setup Time t
SU:STOP
0.26 µs
SDA Data Hold Time t
HD:DAT
0 ns
SDA Data Valid Acknowledge Time t
VD:ACK
(Note 3) 0.05 0.45 µs
SDA Data Valid Time t
VD:DAT
(Note 4) 0.05 0.45 µs
SDA Data Set-Up Time t
SU:DAT
100 ns
SCL Clock Low Period t
LOW
0.5 µs
SCL Clock High Period t
HIGH
0.26 µs
SDA, SCL Fall Time t
f
(Note 1, Note 5, Note 6) 120 ns
SDA, SCL Rise Time t
r
120 ns
SDA, SCL Input Suppression Filter Period t
SP
(Note 2, Note 7) 50 ns
Note 1. Guaranteed by design, not production tested.
Note 2. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low for
time-out. Disable bus timeout via the Fault Enable register 0x03[D6].
Note 3. t
VD:ACK
= SCL LOW to SDA (out) LOW acknowledge time.
Note 4. t
VD:DAT
= minimum SDA output data-valid time following SCL LOW transition.
Note 5. A master device must internally provide an SDA hold time of at least 300ns to ensure an SCL low state.
Note 6. The maximum SDA, SCL and MOSI rise times are 300ns. This allows series protection resistors to be connected between these inputs and
the bus lines without exceeding the maximum allowable rise time. The maximum SDA and MISO fall time is 250ns.
Note 7. The MSL2161 includes input filters on SDA, SCL and ADDR inputs that suppress noise less than 50ns.
Note 8. The GSC input frequency multiplied by (GSCMUL + 1) should not exceed 2.5MHz.
Note 9. When PWMDIRECT = 1 and PHDLYEN = 1 (external PWM with auto phase shift enabled), PWM duty cycles at 0% and 100% are guaranteed,
other duty cycles require minimum on or off time of one full internal oscillator clock cycle and frequency greater than (f
OSC
/10
6
)Hz.
Atmel LED Drivers-MSL2160/MSL2161
16-string, White and RGB LED Drivers with Adaptive Configuration,
EEPROM, and SPI/I
2
C/SMBus Serial Interface