Datasheet
10 Atmel LED Driver-MSL2100
Note1. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low for
t
TIMEOUT
. Disable bus timeout feature for DC operation
Note2. t
VD:ACK
= SCL low to SDA (out) low acknowledge time
Note3. t
VD:DAT
= minimum SDA output data-valid time following SCL low transition
Note4. A master device must internally provide an SDA hold time of at least 300ns to ensure an SCL low state
Note5. The maximum SDA and SCL rise times are 300ns. The maximum SDA fall time is 250ns. This allows series protection resistors to be
connected between SDA and SCL inputs and the SDA/SCL bus lines without exceeding the maximum allowable rise time
Note6. The MSL2100 includes input filters on SDA, SCL, AD0, and AD1 inputs that suppress noise less than 50ns
Note7. Parameter is guaranteed by design, and is not production tested
Note8. Subject to thermal dissipation characteristics of the device
Note9. When mounted according to JEDEC JEP149 and JESD51-12 for a one-layer PCB, θ
JA
= 22°C/W and θ
JC
= 1.3°C/W
PARAMETER CONDITIONS AND NOTES MIN TYP MAX UNIT
AC ELECTRICAL CHARACTERISTICS
OSC initial accuracy
f
OSC
OSCCTRL = 0x04 (f
OSC
=20MHz);
T
A
=25°C
18 20 22 MHz
PHI frequency
f
PHI
(Note 7) 40 10,000 Hz
GSC frequency
f
GSC
(Note 7) 5 MHz
PWM frequency
f
PWM
PWMDIRECT = PWMEN = 1 20 50,000 Hz
PWM duty cycle PWMDIRECT = PWMEN = 1 0 100 %
PHI DLL lock cycles 4
PHI
Cycles
PARAMETER CONDITIONS AND NOTES MIN TYP MAX UNIT
I²C SWITCHING CHARACTERISTICS
SCL clock frequency
1/t
SCL
Bus timeout disabled (Note 1) 0 1,000 kHz
Bus timeout period
t
TIMEOUT
OSCCTRL = 0x04 (f
OSC
=20MHz); T
A
=25°C 27 30 33 ms
STOP to START condition bus free time
t
BUF
0.5 µs
Repeated START condition hold time
t
HD:STA
0.26 µs
Repeated START condition set-up time
t
SU:STA
0.26 µs
STOP condition set-up time
t
SU:STOP
0.26 µs
SDA data hold time
t
HD:DAT
15 ns
SDA data valid acknowledge time
t
VD:ACK
(Note 2) 0.05 0.55 µs
SDA data valid time
t
VD:DAT
(Note 3) 0.05 0.55 µs
SDA data set-up time
t
SU:DAT
100 ns
SCL clock low period
t
LOW
0.5 µs
SCL clock high period
t
HIGH
0.26 µs
SDA, SCL fall time
t
F
(Note 4, Note 5) 120 ns
SDA, SCL rise time
t
R
120 ns
SDA, SCL input suppression lter period
t
SP
(Note 6) 50 ns