Datasheet

32
MSL2023/2024 [DATASHEET]
42063A–LED–02/2013
14.3 I
2
C START and STOP Conditions
Both SCL and SDA remain high when the interface is free. The master signals a transmission with a START condition (S)
by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it
issues a STOP condition (P) by transitioning SDA from low to high while SCL is high. The bus is then free.
Figure 14-4. I
2
C START and STOP conditions.
14.4 I
2
C Acknowledge Bit
The acknowledge bit is a clocked 9th bit which the recipient uses to handshake receipt of each byte of data. The master
generates the 9th clock pulse, and the recipient holds SDA low during the high period of the clock pulse. When the
master is transmitting to the MSL2023/24, the MSL2023/24 pulls SDA low because the MSL2023/24 is the recipient.
When the MSL2023/24 is transmitting to the master, the master pulls SDA low because the master is the recipient.
Figure 14-5. I
2
C acknowledge.
14.5 I
2
C Slave Address
The MSL2023/24 has a 7-bit long slave address, 0b0100000, followed by an eighth bit, the R/W bit. The R/W bit is low for
a write to the MSL2023/24, high for a read from the MSL2023/24. All MSL2023/24 devices have the same slave address;
when using multiple devices and communicating with them through their serial interfaces, make external provision to
route the serial interface to the appropriate device. Note that development systems that use I
2
C often left-shift the
address one position before they insert the R/W bit, and so expect a default address of 0x20 (not 0x40).
SDA
SCL
START
CONDITION
STOP
CONDITION
S
P
SDA
TRANSMITTER
SCL
START
CONDITION
ACKNOWLEDGE
BY RECEIVER
S A
SDA
RECEIVER
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