Datasheet
Table Of Contents
- Features
- Typical Applications
- 1. Introduction
- 2. Ordering Information
- 3. Application Circuit
- 4. Absolute Maximum Ratings
- 5. Electrical Characteristics
- 6. Block Diagram
- 7. Pinout and Pin Description
- 8. Typical Application Circuit
- 9. Detailed Description
- 10. Fault Conditions
- 11. Applications Information
- 12. Control Registers
- 13. Detailed Register Descriptions
- 13.1 RAM (0x00 through 0x1F)
- 13.2 Main String Reference Voltage register (MREF, 0x20)
- 13.3 Color-Adjust String Reference Voltage register (CAREF, 0x21)
- 13.4 Fault Disable register (FAULT, 0x22)
- 13.5 Fault Status register (FAULTSTAT, 0x23), Read Only
- 13.6 Sleep register (SLEEP, 0x24)
- 13.7 Main String Duty Cycle register, High Byte (MDUTYHIGH, 0x34)
- 13.8 Main String Duty Cycle register, Low Byte (MDUTYLOW, 0x35)
- 13.9 Color Adjust String Duty Cycle register, High Byte (CADUTYHIGH, 0x36)
- 13.10 Color Adjust String Duty Cycle register, Low Byte (CADUTYLOW, 0x37)
- 13.11 Efficiency Optimizer Control Register (EOCTRL, 0x40)
- 13.12 Registers 0x60 and 0x61, EEPROM Access
- 14. I²C Serial Interface
- 15. Packaging Information
- 16. Datasheet Revision History
- Table of Contents
27
MSL2023/2024 [DATASHEET]
42063A–LED–02/2013
13.2 Main String Reference Voltage register (MREF, 0x20)
Holds the DAC value that controls the reference voltage for the main string FET source feedback voltage. The reference
voltage equals decimal value of this register times 2mV. The default value for MSREF is 0x64, which equates to
M
REF
= 200mV.
Table 13-2. Main String Reference register (MREF, 0x20), defaults highlighted.
13.3 Color-Adjust String Reference Voltage register (CAREF, 0x21)
Holds the DAC value that controls the reference voltage for the color-adjust string FET source feedback voltage. The
reference voltage equals decimal value of this register times 2mV. The default value for CAREF is 0x64, which equates
to V
CAREF
= 200mV.
Table 13-3. Color-Adjust String Reference register (CAREF, 0x21), defaults highlighted.
13.4 Fault Disable register (FAULT, 0x22)
Bits D0 and D1 control the fault response for the color-adjust string. For fault response behavior see “Fault Conditions”
on page 18. Bit D2 prevents the thermal shutdown fault from pulling FLTB low. Write 0x03 to this register to clear faults;
write 0x00 to re-enable fault response.
Register name Address
Register data
D7 D6 D5 D4 D3 D2 D1 D0
MREF 0x20 MREF[7:0]
DEFAULT = 0x64: M
REF
= 100 * 2mV = 200mV 01100100
M
REF
= 0 2mV = 0V 00000000
M
REF
= 255 * 2mV = 510mV 11111111
Register name Address
Register data
D7 D6 D5 D4 D3 D2 D1 D0
CAREF 0x21 CAREF[7:0]
DEFAULT = 0x64: V
CAREF
= 100 * 2mV = 200mV01100100
V
CAREF
= 0 2mV = 0mV 00000000
V
CAREF
= 255 2mV = 510mV 11111111