Datasheet
Table Of Contents
- Features
- Typical Applications
- 1. Introduction
- 2. Ordering Information
- 3. Application Circuit
- 4. Absolute Maximum Ratings
- 5. Electrical Characteristics
- 6. Block Diagram
- 7. Pinout and Pin Description
- 8. Typical Application Circuit
- 9. Detailed Description
- 10. Fault Conditions
- 11. Applications Information
- 12. Control Registers
- 13. Detailed Register Descriptions
- 13.1 RAM (0x00 through 0x1F)
- 13.2 Main String Reference Voltage register (MREF, 0x20)
- 13.3 Color-Adjust String Reference Voltage register (CAREF, 0x21)
- 13.4 Fault Disable register (FAULT, 0x22)
- 13.5 Fault Status register (FAULTSTAT, 0x23), Read Only
- 13.6 Sleep register (SLEEP, 0x24)
- 13.7 Main String Duty Cycle register, High Byte (MDUTYHIGH, 0x34)
- 13.8 Main String Duty Cycle register, Low Byte (MDUTYLOW, 0x35)
- 13.9 Color Adjust String Duty Cycle register, High Byte (CADUTYHIGH, 0x36)
- 13.10 Color Adjust String Duty Cycle register, Low Byte (CADUTYLOW, 0x37)
- 13.11 Efficiency Optimizer Control Register (EOCTRL, 0x40)
- 13.12 Registers 0x60 and 0x61, EEPROM Access
- 14. I²C Serial Interface
- 15. Packaging Information
- 16. Datasheet Revision History
- Table of Contents

5
MSL2023/2024 [DATASHEET]
42063A–LED–02/2013
Notes: 1. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface when either SDA or SCL is held low for t
TIMEOUT
.
2. SDA Data Valid Acknowledge Time is SCL LOW to SDA (out) LOW acknowledge time.
3. SDA Data Valid Time is minimum SDA output data-valid time following SCL LOW transition.
4. A master device must internally provide an SDA hold time of at least 300ns to ensure an SCL low state.
5. The maximum SDA and SCL rise times is 300ns. The maximum SDA fall time is 250ns. This allows series protection resistors to be connected between SDA
and SCL inputs and the SDA/SCL bus lines without exceeding the maximum allowable rise time.
6. Includes input filters on SDA and SCL that suppress noise less than 50ns.
7. Additional decoupling may be required when pulling current from VCC and/or VDD in noisy environments.
8. 2µs minimum on time, 0% duty cycle is supported. PWM between 0% and 1% not guaranteed.
FBO Full Scale Current 170 255 340 A
FBO LSB Current 1.0 A
Thermal Shutdown Temperature Temperature rising 133 °C
Thermal Shutdown Hysteresis 15 °C
AC Electrical Characteristics
DRV t
OFF
timing R
TOFF
= 45.3k 0.5 s
PWM Input Frequency
PWM1
(8)
60 22,000 Hz
PWM2
(8)
100 500 Hz
PWM Duty Cycle PWM1, PWM2 1 100 %
PWM Duty Cycle Resolution MSL2023 0.024 %
I²C Switching Characteristics
SCL Clock Frequency
(1)
0.05 1,000 kHz
STOP to START Condition Bus Free
Time
t
BUF
0.5 µs
Repeated START condition Hold Time t
HD:STA
0.26 µs
Repeated START condition Setup Time t
SU:STA
0.26 µs
STOP Condition Setup Time t
SU:STOP
0.26 µs
SDA Data Hold Time t
HD:DAT
5 ns
SDA Data Valid Acknowledge Time
(2)
0.05 0.55 µs
SDA Data Valid Time
(3)
0.05 0.55 µs
SDA Data Set-Up Time t
SU:DAT
100 ns
SCL Clock Low Period t
LOW
0.5 µs
SCL Clock High Period t
HIGH
0.26 µs
SDA, SCL Fall Time t
F
(4)
,
(5)
120 ns
SDA, SCL Rise Time t
R
120 ns
SDA, SCL Input Suppression Filter
Period
(6)
50 ns
Bus Timeout t
TIMEOUT
(1)
25 ms
Parameter Symbol Conditions Min. Typ. Max. Unit