Datasheet

Table Of Contents
26
MSL2023/2024 [DATASHEET]
42063A–LED–02/2013
Table 12-2. EEPROM Address register (E2ADDR, 0x60), defaults highlighted.
Table 12-3. EEPROM Control register (E2CTRL, 0x61), defaults highlighted.
13. Detailed Register Descriptions
The MSL2023/24 registers are summarized in “Control Registers” on page 24. Detailed register information follows.
13.1 RAM (0x00 through 0x1F)
32 Bytes of RAM accessible through the I
2
C serial interface. Copy data from RAM into EEPROM (see “EEPROM and
Power-Up Defaults” on page 25) to have the data automatically load into the RAM at power up, and when EN is taken
high.
Table 13-1. RAM (0x00 through 0x1F), defaults undetermined.
Register Address
Register data
D7 D6 D5 D4 D3 D2 D1 D0
E2ADDR 0x60 E2ADDR[6:0]
DEFAULTS 00000000
EEPROM Minimum Address 0x00
0000000
EEPROM Maximum Address 0x51
1010001
Register Address
Register data
D7 D6 D5 D4 D3 D2 D1 D0
E2CTRL 0x61 RWCTRL[2:0]
DEFAULTS 00000000
EEPROM Read / Write Disabled xxxxx000
Read 1 Byte from EEPROM x x x x x 0 0 1
Read 8 Bytes from EEPROM x x x x x 0 1 0
Write 1 Byte to EEPROM x x x x x 0 1 1
Write 8 Bytes to EEPROM x x x x x 1 0 0
Unused
x x x x x 1 0 1
x x x x x 1 1 x
Register name Address
Register data
D7 D6 D5 D4 D3 D2 D1 D0
RAM 0x00 – 0x1F RAM
DEFAULTS X X X X X X X X